Romesh Kumar Nandwana

TL;DR: This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization Noise.

TL;DR: A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs and alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression.

TL;DR: In this article, a high switching frequency multi-phase buck converter architecture using a time-based compensator is presented, which obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller.

TL;DR: This paper presents an ILCM architecture that achieves a NBW of close to FREF/3 with a jitter of 335fsrms at 5GHz, while operating with FREF = 125MHz and consuming 5.3mW.

TL;DR: A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented that employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop to achieve second-order suppression of RO noise, and a digital frequency-tracking loop to continuously tune the oscillator’s free-running frequency.