Showing papers by "Alessandro Trifiletti published in 2007"

Linearization Technique for Source-Degenerated CMOS Differential Transconductors

Abstract: A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-mum process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased by 10 dB (for an input differential signal with a peak amplitude of 0.5 V and for frequencies up to 100 MHz) compared to the traditional source-degenerated transconductor. This THD improvement is achieved with a negligible increase in power consumption.

Analysis of data dependence of leakage current in CMOS cryptographic hardware

Abstract: A novel power analysis technique for CMOS cryptographic hardware based on leakage power consumption measurements is presented. Algorithms and models to predict the input vector for maximum and minimum leakage currentallin CMOS gates are reviewed. Extensive transistor level simulations on a simple CMOS crypto core are presented. Leakage current measurements carried out on an ASIC for cryptographic applications implemented in a 0.13 um CMOS technology are reported. The results of this work show that leakage current can be exploited as a side channel by an attacker to extract information about the secret key in cryptographic hardware implemented in short channel CMOS technologies.

Low Voltage CMOS Current and Voltage References without Resistors

Abstract: The authors describe low voltage current and voltage references which only use MOSFETs in strong inversion and pnp substrate transistors; both the references exhibit very good performance in terms of power supply rejection and do not require compensation capacitances; the minimum supply voltage is about 0.8V for the current reference and 1.2V for the voltage reference.

Testing power-analysis attack susceptibility in register-transfer level designs

Abstract: The susceptibility of cryptographic devices to attacks based on power analysis can be both significantly and efficiently tested at early design steps. The results from a real case application show the advantages of the approach.

Sub-1V CMOS OTA with body-driven gain boosting

Abstract: A low-voltage CMOS amplifier exploiting a new body-driven gain boosting technique is described. Compared to the standard gain boosting approach, the proposed one reduces the minimum supply by one threshold voltage in the single structure, and by two thresholds in an amplifier exploiting two complementary versions. Simulations using a 130-nm process show that a 0.9-V supply voltage is adequate to obtain a single-stage rail-to-rail amplifier with a 55-dB gain, which is 17 dB higher than that achieved by the same amplifier but using the traditional low-voltage cascode approach.

The Universal Circuit Simulator: A Mixed-Signal Approach to $n$ -Port Network and Impedance Synthesis

Abstract: A mixed-signal universal architecture able to emulate the behavior of an n-port analog circuit is presented. It exploits second-generation current conveyors as analog input/output blocks and a field programmable gate array circuit as digital processing element. A prototype is also discussed for the specific case of a two-port network synthesis and experimental results in agreement with expected ones are provided.

CCII-based high-valued inductance simulators with minumum number of active elements

Abstract: This paper presents novel CCII-based circuit solutions for the implementation of grounded and floating inductance simulators for integrable low frequency applications. The circuits, implementing a minimum number of active components, allow the reduction and, in theory, the zeroing of the undesired inductance series resistance, with consequent increase of operating range towards the low frequencies. A novel idea to increase the value of the equivalent inductance achievable with CCII based topologies is presented. Simulation results, confirming the theoretical expectations, are also included.

A Dynamic and Differential CMOS Lookup Table with Data Independent Power Consumption for Cryptographic Applications on Chip Cards

Abstract: Attacks based on a differential power analysis (DPA) are a main threat when designing cryptographic functions for implementation on chip cards. In this paper, a dynamic and differential lookup table (LUT) is presented and evaluated on a case study simulation. The proposed circuit shows a power consumption independent from the input data and can be employed to implement combinatorial functions in cryptographic processors when a high resistance against tampering is required. A typical application is the design of nonlinear functions (for example, substitution boxes) since protecting them with less expensive countermeasures (for example, random masking) implies a significant overhead. In the adopted case study, a 1.02 percent spread in the power consumption has been obtained when parasitic capacitances are taken into account. Moreover, a comparison with a static complementary metal-oxide semiconductor implementation shows an acceptable overhead in terms of area and power consumption.

150 μA CMOS Transconductor with 82 dB SFDR

Abstract: A CMOS high-linearity transconductor useful for IC filtering applications is presented. It is based on a feedback unity-gain amplifier driving a resistor to achieve linear voltage-to-current conversion. Simulation results are provided on a design example using a 0.35-mum technology, powered from a 3.3V supply, and using a total dc current of 150 muA. The 3-dB bandwidth was 630 MHz and HD3, onto a load resistor of 20kOmega, was -82 dB at 1MHz.

CMOS Miller OTA with body-biased output stage

Abstract: A bias technique for low-voltage class AB amplifiers is presented. The approach exploits the bulk terminal to set the output quiescent current of a two-stage class-AB CMOS OTA in a reliable manner and without reducing the maximum swing capability. Simulations on a designed example using a 0.25-mum CMOS process show the viability of the approach.

Very low voltage CMOS two-stage amplifier

Abstract: A minimum-supply rail-to-rail differential stage architecture is presented. It exhibits easy cascading features and unlike previous similar solutions does not critically affect CMRR. Starting from this block, a fully-differential two-stage amplifier is designed using 0.7-V supply in a 130-nm CMOS technology. Simulations show a 47-dB dc differential gain with a gain-bandwidth product of 700 MHz, and 70-dB CMRR at dc, under a total nominal current consumption lower than 2 mA.

A statistical model of logic gates for Monte Carlo simulation including on-chip variations

Abstract: Process variations are becoming a paramount design problem in nano-scale VLSI. We present a framework for the statistical model of logic gates that describes both inter-die and intra-die variations of performance parameters such as propagation delay and leakage currents. This allows fast but accurate behavioral-level Monte-Carlo simulations, that could be useful for full-custom digital design optimization and yield prediction, and enables the development of a yield-aware digital design flow. The model can incorporate correlation between mismatch parameters and dependence on distance and position, and can be extracted by fitting of Monte-Carlo transistor level simulations. An example implementation using Verilog-A hardware description language in Cadence environment is presented.

A sample-and-hold circuit with very low gain error for time interleaving applications

Abstract: A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is replaced with a couple of low gain amplifiers in feedback mode. Simulation results show that the proposed active-feedback voltage follower allows a very low gain error with low sensitivity to circuit mismatches and a limited distortion penalty. This makes it suitable to be used in time interleaving applications with distributed sampling.

Design, realization, and test of a 900 MHZ ceramic oscillator

Abstract: The design of a 900 MHz ceramic oscillator, delivering a power of 10 dBm, has been carried out by using the negative-resistance condition. A new procedure based on the Nyquist criterion, implemented within microwave CADs has been used to test the onset of oscillations at the desired frequency and the presence of spurious oscillation. An excellent agreement between nonlinear simulations and measurements performed on a prototype has been observed. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1713–1717, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22528

Mismatch-tolerant, Continuous Time, Gain Enhanced Amplifiers

Abstract: We describe the first ever reported continuous time, gain enhanced voltage amplifiers which are almost insensitive to mismatch of active devices. Though the proposed approach is general, as a preliminary test we have designed a voltage amplifier in a standard 0.35mum CMOS process; Monte Carlo simulations demonstrate both a significant gain enhancement and its robustness against spread of process parameters.

Mismatch tolerant, continuous time, rail to rail, gain enhanced CMOS amplifiers

Abstract: We describe continuous time, rail to rail, gain enhanced voltage amplifiers with a gain error which is almost insensitive to mismatch of active devices. Though the proposed approach is general, as a preliminary test we have designed a voltage amplifier in a standard 0.35 mum CMOS process; Montecarlo and AC simulations demonstrate a significant gain enhancement, its robustness against spread of process parameters and a small output resistance.