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Amit Chhabra
Researcher at STMicroelectronics
Publications - 16
Citations - 230
Amit Chhabra is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Voltage & CMOS. The author has an hindex of 6, co-authored 16 publications receiving 229 citations.
Papers
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Journal ArticleDOI
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization
David Jacquet,Frederic Hasbani,Philippe Flatresse,Robin Wilson,Franck Arnaud,Giorgio Cesana,Thierry Di Gilio,Christophe Lecocq,Tanmoy Roy,Amit Chhabra,Chiranjeev Grover,Olivier Minez,Jacky Uginet,Guy Durieu,Cyril Adobati,Davide Casalotto,Frederic Nyer,Patrick Menut,Andreia Cathelin,Indavong Vongsavady,Philippe Magarshack +20 more
TL;DR: The implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology are presented.
Proceedings Article
2.6GHz ultra-wide voltage range energy efficient dual A9 in 28nm UTBB FD-SOI
David Jacquet,Giorgio Cesana,Philippe Flatresse,Franck Arnaud,P. Menut,Frederic Hasbani,T. Di Gilio,Christophe Lecocq,Tanmoy Roy,Amit Chhabra,C. Grover,O. Minez,J. Uginet,Guy Durieu,F. Nyer,C. Adobati,Robin Wilson,D. Casalotto +17 more
TL;DR: The implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology are presented, enabling an extremely energy efficient implementation.
Patent
Multi-supply dual port register file
Amit Chhabra,Kailash Digari +1 more
TL;DR: In this paper, a multi-supply dual port register file is proposed for transferring data between two power domains that operate on different voltages or frequencies, where the register file comprises a memory cell that stores the data transferred between the domains.
Journal ArticleDOI
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
TL;DR: A low-energy power-ON reset (POR) circuit, designed in the 40-nm CMOS technology within 10.6-μm2 area, enabled 27× reduction in the energy consumed by the SRAM array supply during periphery power-up in typical conditions.
Patent
Apparatus and method for testing shadow logic
TL;DR: In this article, a system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic blocks.