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Christophe Lecocq
Researcher at STMicroelectronics
Publications - 10
Citations - 191
Christophe Lecocq is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Voltage & Voltage source. The author has an hindex of 5, co-authored 9 publications receiving 191 citations.
Papers
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Journal ArticleDOI
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization
David Jacquet,Frederic Hasbani,Philippe Flatresse,Robin Wilson,Franck Arnaud,Giorgio Cesana,Thierry Di Gilio,Christophe Lecocq,Tanmoy Roy,Amit Chhabra,Chiranjeev Grover,Olivier Minez,Jacky Uginet,Guy Durieu,Cyril Adobati,Davide Casalotto,Frederic Nyer,Patrick Menut,Andreia Cathelin,Indavong Vongsavady,Philippe Magarshack +20 more
TL;DR: The implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology are presented.
Proceedings Article
2.6GHz ultra-wide voltage range energy efficient dual A9 in 28nm UTBB FD-SOI
David Jacquet,Giorgio Cesana,Philippe Flatresse,Franck Arnaud,P. Menut,Frederic Hasbani,T. Di Gilio,Christophe Lecocq,Tanmoy Roy,Amit Chhabra,C. Grover,O. Minez,J. Uginet,Guy Durieu,F. Nyer,C. Adobati,Robin Wilson,D. Casalotto +17 more
TL;DR: The implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology are presented, enabling an extremely energy efficient implementation.
Proceedings ArticleDOI
28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications
R. Ranica,Nicolas Planes,V. Huard,Olivier Weber,D. Noblet,Damien Croain,F. Giner,S. Naudet,P. Mergault,S. Ibars,Alexandre Villaret,M. Parra,Sebastien Haendler,M. Quoirin,Florian Cacho,C. Julien,F. Terrier,Lorenzo Ciampolini,David Turgis,Christophe Lecocq,Franck Arnaud +20 more
TL;DR: The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology and Vmin retention below 0.4V is demonstrated, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.
Patent
Method and System for Managing the Power Supply of a Component
TL;DR: In this article, a method and system for managing the power supply of a component and of a memory cooperating with the component is described, where the component and the memory are powered with a first variable power supply source having a first power supply voltage level greater than a minimum operating voltage of the memory.
Journal ArticleDOI
Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node
Lorenzo Ciampolini,Siddharth Gupta,Olivier Callen,Amit Chhabra,Dibya Dipti,Sebastien Haendler,Shishir Kumar,Daniel Noblet,Pierre Malinge,Nicolas Planes,David Turgis,Christophe Lecocq,Shamsi Azmi +12 more