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David Jacquet
Researcher at STMicroelectronics
Publications - 7
Citations - 172
David Jacquet is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Digital signature & Scan chain. The author has an hindex of 4, co-authored 7 publications receiving 172 citations.
Papers
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Journal ArticleDOI
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization
David Jacquet,Frederic Hasbani,Philippe Flatresse,Robin Wilson,Franck Arnaud,Giorgio Cesana,Thierry Di Gilio,Christophe Lecocq,Tanmoy Roy,Amit Chhabra,Chiranjeev Grover,Olivier Minez,Jacky Uginet,Guy Durieu,Cyril Adobati,Davide Casalotto,Frederic Nyer,Patrick Menut,Andreia Cathelin,Indavong Vongsavady,Philippe Magarshack +20 more
TL;DR: The implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology are presented.
Proceedings Article
2.6GHz ultra-wide voltage range energy efficient dual A9 in 28nm UTBB FD-SOI
David Jacquet,Giorgio Cesana,Philippe Flatresse,Franck Arnaud,P. Menut,Frederic Hasbani,T. Di Gilio,Christophe Lecocq,Tanmoy Roy,Amit Chhabra,C. Grover,O. Minez,J. Uginet,Guy Durieu,F. Nyer,C. Adobati,Robin Wilson,D. Casalotto +17 more
TL;DR: The implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology are presented, enabling an extremely energy efficient implementation.
Patent
Method and System for Managing the Power Supply of a Component
TL;DR: In this article, a method and system for managing the power supply of a component and of a memory cooperating with the component is described, where the component and the memory are powered with a first variable power supply source having a first power supply voltage level greater than a minimum operating voltage of the memory.
Patent
Method, device and article to test digital circuits
David Jacquet,Didier Fuin +1 more
TL;DR: In this article, checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuits via scan chain.
Patent
Method and device to test digital circuits
David Jacquet,Didier Fuin +1 more
TL;DR: In this article, checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuits via scan chain.