G
Giorgio Cesana
Researcher at STMicroelectronics
Publications - 5
Citations - 340
Giorgio Cesana is an academic researcher from STMicroelectronics. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 5, co-authored 5 publications receiving 337 citations.
Papers
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Journal ArticleDOI
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization
David Jacquet,Frederic Hasbani,Philippe Flatresse,Robin Wilson,Franck Arnaud,Giorgio Cesana,Thierry Di Gilio,Christophe Lecocq,Tanmoy Roy,Amit Chhabra,Chiranjeev Grover,Olivier Minez,Jacky Uginet,Guy Durieu,Cyril Adobati,Davide Casalotto,Frederic Nyer,Patrick Menut,Andreia Cathelin,Indavong Vongsavady,Philippe Magarshack +20 more
TL;DR: The implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology are presented.
Proceedings ArticleDOI
UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency
TL;DR: UTBB FD-SOI technology has become mainstream within STMicroelectronics enabling it to provide already at 28nm node a real differentiation in terms of flexibility, cost and energy efficiency with respect to any process available on the market.
Proceedings ArticleDOI
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology
P. Flatresse,Bastien Giraud,Jean-Philippe Noel,Bertrand Pelloux-Prayer,Franck Giner,D. Arora,Franck Arnaud,Nicolas Planes,J. Le Coz,Olivier P. Thomas,Sylvain Engels,Giorgio Cesana,Robin Wilson,Pascal Urard +13 more
TL;DR: This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and introduces extended body bias (BB) design techniques to take advantage of specific features of the UTBB technology to overcome the +/-300mV BB range limitation of conventional bulk technologies.
Proceedings ArticleDOI
Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications
Bertrand Pelloux-Prayer,Milovan Blagojevic,Olivier Thomas,Amara Amara,Andrei Vladimirescu,Borivoje Nikolic,Giorgio Cesana,Philippe Flatresse +7 more
TL;DR: In this article, a planar FD implementation of a representative design offers 1.6×-7× speedup compared to bulk across a range of supply voltages, with better power efficiency across use cases than any of the conventional bulk CMOS flavors.
Proceedings Article
2.6GHz ultra-wide voltage range energy efficient dual A9 in 28nm UTBB FD-SOI
David Jacquet,Giorgio Cesana,Philippe Flatresse,Franck Arnaud,P. Menut,Frederic Hasbani,T. Di Gilio,Christophe Lecocq,Tanmoy Roy,Amit Chhabra,C. Grover,O. Minez,J. Uginet,Guy Durieu,F. Nyer,C. Adobati,Robin Wilson,D. Casalotto +17 more
TL;DR: The implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology are presented, enabling an extremely energy efficient implementation.