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Design Of Analog Cmos Integrated Circuits

Novel pervasive devices such as smart surveillance cameras and autonomous micro-UAVs could greatly benefit from the availability of a computing device supporting embedded computer vision at a very low power budget. To this end, we propose PULP (Parallel processing Ultra-Low Power platform), an architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability that exploit the capabilities of the STMicroelectronics UTBB FD-SOI 28nm technology. We show that PULP performance can be scaled over a 1x-354x range, with a peak theoretical energy efficiency of 211 GOPS/W. We present performance results for several demanding kernels from the image processing and vision domain, with post-layout power modeling: a motion detection application that can run at an efficiency up to 192 GOPS/W (90 % of the theoretical peak); a ConvNet-based detector for smart surveillance that can be switched between 0.7 and 27fps operating modes, scaling energy consumption per frame between 1.2 and 12mJ on a 320 ×240 image; and FAST + Lucas-Kanade optical flow on a 128 ×128 image at the ultra-low energy budget of 14 μJ per frame at 60fps.

PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision

The most important application of ICs, today, is most probably the lnternet-of-Things It involves sensor nodes and communications at the lowest-possible power levels Similar low power levels are required for the next-generation smart-phones as images and video become increasing requirements, in phone, body-worn, and automotive applications Whatever technology is used, portability requires reduced power consumption

1.3 Analog CMOS from 5 micrometer to 5 nanometer

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human–Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from −1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range −40 °C to 120 °C exploiting −1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors with comparable performance, including those implemented in 28 nm technology, our platform provides 1.4× to 3.7× better energy efficiency.

A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

Temperature plays a crucial role in deciding SRAM performance especially at very low voltage. SRAM bitcell has conflicting constraints of write-ability and stability at cold (−40°C typically) and hot temperature (125°C typically) respectively. In order to reduce SRAM minimum operating voltage (VMIN), write and stability assist schemes are deployed. Fully-Depleted SOI (FDSOI) technology offers single P-well SRAM bitcell, where a single voltage can be used to adjust the state of the body (or P-well) of all bitcell devices. This voltage can vary from −1.1V to +1.1V. In this paper, we present detailed architecture and implementation of the low-power adaptive memory sub-system that modulates body bias voltage based on the junction temperature to reduce SRAM VMIN. The body is biased to positive voltages up to +1.1V to boost write-ability at cold temperatures and up to −1.1V to boost stability at hot temperatures. In addition, the system selects appropriate assist scheme based on temperature information. We present the dynamic simulation based functional verification environment using temperature and voltage-aware memory models that are compliant with IEEE 1801. We gained 50mV in SRAM VMIN thereby allowing 0.55V operation using high density 0.120μm2 single P-well bitcell in 28nm planar Ultra-Thin Box and Body (UTBB) FDSOI CMOS technology. We also gained 18% dynamic power during regular temperature range of 10°C and 75°C. In addition, due to forward body bias at cold temperature, we gained 30% in SRAM access time.

Temperature-based adaptive memory sub-system in 28nm UTBB FDSOI

The design of Ultra-Low Power clock reference systems with highly energy-efficient operations is a key concept to achieve autonomous Internet-of-Things applications. In this work, a System-on-Chip is presented, embedding an area-efficient ultra-low voltage clock reference generator built on a digitally controlled leakage-based Ring Oscillator. Through a relocking scheme using a 222 Hz external quartz reference, an associated digital compensation circuit ensures a stable output frequency of 32.768 kHz over inherent Process, Voltage and Temperature variations. The whole design has been fabricated in 28 nm FD-SOI technology and operates at a fixed supply voltage V dd of 0.5 V. By combining Ultra-Low Power techniques, a 15 nW power consumption is achieved for the Oscillator and 125 nW for the digital compensation. The circuit area of the proposed clock source is 56.2 μm x 29.1 μm. A 90 ppm/V voltage accuracy has been measured over 10 packaged dies for V dd ± 8%. A temperature accuracy of 1.9 ppm/°C is also reported from 0 °C to 50 °C. Lastly, the long-term frequency stability is characterized by an Allan deviation floor of 0.1 ppm.

A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI

In this chapter we will discuss about the choice of generating body-bias voltage generation inside or outside of the SoCs. For both cases advantages and disadvantages will be highlighted. The second step of this part treats of the load seen by a Body-Bias GENerator (BBGEN), embedded or not. These exercises will be helpful to determine the list of main specifications that should have a BBGEN. Each specification elements will be detailed. As for any analogue circuit, knowledge of the output load is definitely essential to realize a successful design. After that we will elaborate on some way to build and design a BBGEN and how to implement it at SoC level.

Thierry Di Gilio

Papers

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

Temperature-based adaptive memory sub-system in 28nm UTBB FDSOI

A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI

Body-Bias Voltage Generation