International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The surface-potential-based compact transistor model, MOS Model 20 (MM20), has been extended with a quasi-saturation, an effect that is typical for LDMOS devices with a long drift region As a result, MM20 extends its application range from low-voltage LDMOS devices up to high-voltage LDMOS devices of about 100V In this paper, the new dc model of MM20, including quasi-saturation, is presented The addition of velocity saturation in the drift region ensures the current to be controlled by either the channel region or the drift region A comparison with dc measurements on a 60-V LDMOS device shows that the new model provides an accurate description in all regimes of operation, ranging from subthreshold to superthreshold, in both the linear and saturation regime Thus, owing to the inclusion of quasi-saturation also the regime of high-gate and high-drain bias conditions for high-voltage LDMOS devices is accurately described

Compact modeling of high-voltage LDMOS devices including quasi-saturation

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20nm FinFET technologies

This paper is about the compared performance investigation of various structures of Hetero-Dielectric (HD) triple-gate FinFETs with different gate oxides in terms of Double Hetero Gate Oxide (DHGO), Triple Hetero Gate Oxide (THGO) and Quadruple Hetero Gate Oxide (QHGO) to produce lower leakage current, higher Ion/Ioff ratio, higher gm/gd and also lower Drain Induced Barrier Lowering (DIBL) than those of a conventional triple-gate FinFET. Among all of them, the best results are explored for the DHGO FinFET structure. In DHGO FinFET structure, a high-κ dielectric (κ = 22) is used on the top oxide to increase the gate control and a low-k dielectric (κ = 3.9) is used over silicon body owing to the compatibility of lattice constant of SiO2 and silicon. Mode-space drift-diffusion (DD_MS) model coupled with Schrodinger equation has been utilized in order to analyze the proposed and conventional structures in three dimensional (3D) simulation domain. Interestingly, by decreasing the thickness of the oxide layer and increasing the permittivity coefficient, the leakage current decreases, thus increasing the Ion/Ioff ratio. The DHGO FinFET structure is found to exhibit higher Ion/Ioff, lower DIBL and higher gm/gd ratio, thus proving performance superiority over the other conventional junctionless FinFET and also MOSFETs.

Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering

This paper presents a single-ended low-power 7T SRAM cell in FinFET technology. This cell enhances read performance by isolating the storage node from the read path. Moreover, disconnecting the feedback path of the cross-coupled inverters during the write operation enhances WSNM by nearly 7.7X in comparison with the conventional 8T SRAM cell. By using only one bit-line, this cell reduces power consumption and PDP compared to the conventional 8T SRAM cell by 82% and 35%, respectively.

A low-power single-ended SRAM in FinFET technology

http://faratarjome.ir/u/media/shopping_files/store-EN-1428386559-2028.pdf

A partial-SOI LDMOSFET with triangular buried-oxide for breakdown voltage improvement

In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved.

Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage

In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.

Process variation study of Ground Plane SOI MOSFET

In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM), read current, and standby power. The structures include SOI with ground plane in substrate (SOI-GPS), SOI with ground plane in buried oxide (SOI-GPB), and SOI without ground plane (SOI-WGP). In addition, the variations of the SRAM characteristics due to channel length and thin-film thickness variations are investigated. The results show that the SOI-GPS structure is more resistant against the process variations when compared to the other two structures.

Behzad Ebrahimi

Papers

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20nm FinFET technologies

A partial-SOI LDMOSFET with triangular buried-oxide for breakdown voltage improvement

Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage

Process variation study of Ground Plane SOI MOSFET

Ground plane SOI MOSFET based SRAM with consideration of process variation