Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (∼10−8 W) to massive data centers (∼109 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces. 
Open image in new window

/pdf/energy-dissipation-and-transport-in-nanoscale-devices-2fj1ezlyhz.pdf

Energy dissipation and transport in nanoscale devices

Understanding energy dissipation and transport in nanoscale structures is of great importance for the design of energy-efficient circuits and energy-conversion systems. This is also a rich domain for fundamental discoveries at the intersection of electron, lattice (phonon), and optical (photon) interactions. This review presents recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures. First, the landscape of power usage from nanoscale transistors (~10^-8 W) to massive data centers (~10^9 W) is surveyed. Then, focus is given to energy dissipation in nanoscale circuits, silicon transistors, carbon nanostructures, and semiconductor nanowires. Concepts of steady-state and transient thermal transport are also reviewed in the context of nanoscale devices with sub-nanosecond switching times. Finally, recent directions regarding energy transport are reviewed, including electrical and thermal conductivity of nanostructures, thermal rectification, and the role of ubiquitous material interfaces.

/pdf/energy-dissipation-and-transport-in-nanoscale-devices-17sw2ubrhz.pdf

Energy Dissipation and Transport in Nanoscale Devices

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 /spl mu/m) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects.

/pdf/fabrication-and-analysis-of-deep-submicron-strained-si-n-2wp4p6e07d.pdf

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Performance and power are two primary design issues for systems ranging from server computers to handhelds. Performance is affected by both temperature and supply voltage because of the temperature and voltage dependence of circuit delay. Furthermore, as semiconductor technology scales down, leakage power's exponential dependence on temperature and supply voltage becomes significant. Therefore, future design studies call for temperature and voltage aware performance and power modeling. In this paper, we study microarchitecture-level temperature and voltage aware performance and power modeling. We present a leakage power model with temperature and voltage scaling, and show that leakage and total energy vary by 38% and 24%, respectively, between 65/spl deg/C and 110/spl deg/C. We study thermal runaway induced by the interdependence between temperature and leakage power, and demonstrate that without temperature-aware modeling, underestimation of leakage power may lead to the failure of thermal controls, and overestimation of leakage power may result in excessive performance penalties of up to 5.24%. All of these studies underscore the necessity of temperature-aware power modeling. Furthermore, we study optimal voltage scaling for best performance with dynamic power and thermal management under different packaging options. We show that dynamic power and thermal management allows designs to target at the common-case thermal scenario among benchmarks and improves performance by 6.59% compared to designs targeted at the worst case thermal scenario without dynamic power and thermal management. Additionally, the optimal V/sub dd/ for the best performance may not be the largest V/sub dd/ allowed by the given packaging platform, and that advanced cooling techniques can improve throughput significantly.

/pdf/temperature-and-supply-voltage-aware-performance-and-power-5ds92tnkg5.pdf

Temperature and supply Voltage aware performance and power modeling at microarchitecture level

There are numerous methods for measuring the temperature of an operating semiconductor device. The methods can be broadly placed into three generic categories: electrical, optical, and physically contacting. The fundamentals underlying each of the categories are discussed, and a review of the variety of techniques within each category is given. Some of the advantages and disadvantages as well as the spatial, time, and temperature resolution are also provided.

Temperature measurements of semiconductor devices - a review

Self-heating is an important issue for SOI CMOS, and hence, so is its characterization and modeling. This paper sets out how the critical parameters for modeling, i.e., thermal resistance and thermal time-constants, may be obtained using purely electrical measurements on standard MOS devices. A summary of the circuit level issues is presented, and the physical effects contributing to thermally related MOSFET behavior are discussed. A new thermal extraction technique is presented, based on an analytically derived expression for the electro-thermal drain conductance in saturation. Uniquely, standard MOSFET structures can be used, eliminating errors due to additional heat flow through special layouts. The conductance technique is tested experimentally and results are shown to be in excellent agreement with thermal resistance values obtained from noise thermometry and gate resistance measurements using identical devices. It is demonstrated that the conductance technique can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.

Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques

With growing WCDMA adoption there is a strong demand to reduce the cost of WCDMA terminals. Contributing to the relatively high WCDMA terminal cost is the low integration of today's WCDMA radios. Since WCDMA is an FDD system the transmitter and receiver are on simultaneously. A duplexer is used to isolate the receiver from the transmit signal but the isolation of small low-cost duplexers is limited, with a guaranteed isolation at the TX frequency of not more than 52dB. For a Class-3 terminal with 2dB TX path loss due to duplexer and switch, the power at the PA output is +26dBm and the receiver will see a TX leakage of up to -26dBm. Today's state-of- the-art WCDMA transceivers deal with the TX blocking problem by using an external TX SAW filter to eliminate TX noise in the RX band and an external LNA and RX SAW filter to achieve sufficient RX linearity. A typical tri-band transceiver requires 6 SAW filters and 3 LNAs. The tri-band WCDMA transceiver presented here eliminates all external SAW filters and LNAs and achieves excellent performance with standard low-cost duplexers.

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

This paper examines the influence of the static and dynamic electrothermal behavior of silicon-on-insulator (SOI) CMOS transistors on a range of primitive analog circuit cells. In addition to the more well-known self-heating close-range thermal coupling effects are also examined. Particular emphasis is given to the impact of these effects on drain current mismatch due to localized temperature differences. Dynamic electrothermal behavior in the time and frequency domains is also considered, measurements and analyses are presented for a simple amplifier stage, current mirrors, a current output D/A converter, and ring oscillators fabricated in a 0.7-/spl mu/m SOI CMOS process. It is shown that circuits which rely strongly on matching, such as the current mirrors or D/A converter, are significantly affected by self-heating and thermal coupling. Anomalies due to self-heating are also clearly visible in the small-signal characteristics of the amplifier stage. Self-heating effects are less significant for fast switching circuits. The paper demonstrates how circuit-level simulations can be used to predict undesirable nonisothermal operating conditions during the design stage.

Impact of self-heating and thermal coupling on analog circuits in SOI CMOS

A mixer-first receiver (RX) with enhanced selectivity and high dynamic range is proposed, targeting to remove surface acoustic-wave-filters in mobile phones and cover all frequency bands up to 6 GHz. Capacitive negative feedback across the baseband (BB) amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the BB amplifier, which is upconverted to the RF port to obtain steeper RF bandpass filter roll-off and reduced distortion. This paper explains the circuit principle and analyzes RX performance. A prototype chip fabricated in 45-nm partially depleted silicon on insulator (SOI) technology achieves high out-of-band linearity (input-referred third-order intercept point (IIP3) = 39 dBm and input-referred second-order intercept point (IIP2) = 88 dB) combined with sub-3-dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz.

/pdf/enhanced-selectivity-high-linearity-low-noise-mixer-first-138rhbj1zt.pdf

Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback

This paper examines some implications for analogue design of using body ties as a solution to the problem of floating body effects in partially-depleted (PD) SOI technologies. Measurements on H-gate body-tied structures in a 0.7-/spl mu/m SOI process indicate body-tie series resistances increasing into the M/spl Omega/ region. Both circuit simulation and measurement results reveal a delayed but sharper kink effect as this resistance increases. The consequences of this effect are shown in the context of a simple amplifier configuration, resulting in severe bias-dependent degradation in the small signal gain characteristics as the body-tie resistance enters the M/spl Omega/ region. It is deduced that imperfectly body tied devices may be worse for analogue design than using no body-tie at all.

Bernard Mark Tenbroek

Papers

Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

Impact of self-heating and thermal coupling on analog circuits in SOI CMOS

Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback

The effect of body contact series resistance on SOI CMOS amplifier stages