Bernhard Goll

TL;DR: A comparator in a low-power 65-nm complementary metal-oxide-semiconductor process (only standard transistors with threshold voltage Vt ap 0.4 V were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.65-V supply.

TL;DR: Clocked regenerative comparators, which use positive feedback of a latch to force a fast decision, are used for many applications and are designed to extract every 4th bit of a 40Gb/s data stream.

TL;DR: This comparator has 2 active-load PMOS transistors that can be used to reset the output nodes to the supply level and an NMOS transistor added in the clock line controls the active loads to avoid additional reset switches and continuously biased load transistors.

TL;DR: In this article, a comparator, fabricated in a 1.5 V/0.12 mum CMOS process, is presented, where the commonly separated reset and active-load transistors of typical comparators are combined.

TL;DR: In this article, the authors present modulators developed in the projects "HELIOS" and "UK Silicon Photonics" integration with modulator driver to produce the first silicon modulator fully integrated with BiCMOS, and multiplexed photonic crystal modulators for ultra-low power operation.