The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or 'high K' gate oxides such as hafnium oxide and hafnium silicate. Little was known about such oxides, and it was soon found that in many respects they have inferior electronic properties to SiO2 ,s uch as a tendency to crystallise and a high concentration of electronic defects. Intensive research is underway to develop these oxides into new high quality electronic materials. This review covers the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects. The use of high K oxides in capacitors of dynamic random access memories is also covered.

/pdf/high-dielectric-constant-oxides-cotu2e70vd.pdf

High dielectric constant oxides

On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

Complementary resistive switches for passive nanocrossbar memories

Lasing is experimentally demonstrated in a direct bandgap GeSn alloy, grown directly onto Si(001). The authors observe a clear lasing threshold as well as linewidth narrowing at low temperatures.

/pdf/lasing-in-direct-bandgap-gesn-alloy-grown-on-si-515b98x7i8.pdf

Lasing in direct-bandgap GeSn alloy grown on Si

The conduction and valence band offsets between amorphous LaAlO3 and silicon have been determined from x-ray photoelectron spectroscopy measurements. These films, which are free of interfacial SiO2, were made by molecular-beam deposition. The band line-up is type I with measured band offsets of 1.8±0.2 eV for electrons and 3.2±0.1 eV for holes. The band offsets are independent of the doping concentration in the silicon substrate as well as the amorphous LaAlO3 film thickness. These amorphous LaAlO3 films have a bandgap of 6.2±0.1 eV.

/pdf/measurement-of-the-band-offsets-between-amorphous-laalo3-and-2j9yvsohme.pdf

Measurement of the band offsets between amorphous LaAlO3 and silicon

In this letter, we propose a heterostructure design for tunnel field effect transistors with two low direct bandgap group IV compounds, GeSn and highly tensely strained Ge in combination with ternary SiGeSn alloy. Electronic band calculations show that strained Ge, used as channel, grown on Ge 1−xSnx (x > 9%) buffer, as source, becomes a direct bandgap which significantly increases the tunneling probability. The SiGeSn ternaries are well suitable as drain since they offer a large indirect bandgap. The growth of such heterostructures with the desired band alignment is presented. The crystalline quality of the (Si)Ge(Sn) layers is similar to state-of-the-art SiGe layers.

/pdf/band-engineering-and-growth-of-tensile-strained-ge-si-gesn-1e5b7q35pq.pdf

Band engineering and growth of tensile strained Ge/(Si)GeSn heterostructures for tunnel field effect transistors

A mechanism of strain relief of H+ ion implanted and annealed pseudomorphic Si1−xGex/Si(100) heterostructures grown by molecular beam epitaxy is proposed and analyzed Complete strain relaxation was obtained at temperatures as low as 800 °C and the samples appeared free of threading dislocations within the SiGe layer to the limit of transmission electron microscopy analysis In our model, H filled nanocracks are assumed to generate dislocation loops, which glide to the interface where they form strain relieving misfit segments On the basis of this assumption, the conditions for efficient strain relaxation are discussed

/pdf/strain-relaxation-mechanism-for-hydrogen-implanted-si1-xgex-3pa19h2ap4.pdf

Strain relaxation mechanism for hydrogen-implanted Si1−xGex/Si(100) heterostructures

The recent observation of a fundamental direct bandgap for GeSn group IV alloys and the demonstration of low temperature lasing provide new perspectives on the fabrication of Si photonic circuits. This work addresses the progress in GeSn alloy epitaxy aiming at room temperature GeSn lasing. Chemical vapor deposition of direct bandgap GeSn alloys with a high Γ- to L-valley energy separation and large thicknesses for efficient optical mode confinement is presented and discussed. Up to 1 μm thick GeSn layers with Sn contents up to 14 at. % were grown on thick relaxed Ge buffers, using Ge2H6 and SnCl4 precursors. Strong strain relaxation (up to 81%) at 12.5 at. % Sn concentration, translating into an increased separation between Γ- and L-valleys of about 60 meV, have been obtained without crystalline structure degradation, as revealed by Rutherford backscattering spectroscopy/ion channeling and transmission electron microscopy. Room temperature reflectance and photoluminescence measurements were performed to ...

/pdf/direct-bandgap-group-iv-epitaxy-on-si-for-laser-applications-kvymymyv1a.pdf

Direct Bandgap Group IV Epitaxy on Si for Laser Applications

Strain relaxed Si1−xGex layers on Si(1 0 0) are used as virtual substrates for the growth of e.g. Si/Si1−xGex quantum well structures. We investigated the effects of H+ and He+ ion implantation and subsequent annealing on pseudomorphic Si 1−x Ge x / Si (1 0 0) heterostructures grown by molecular beam epitaxy (MBE). A narrow defect band is generated by ion implantation slightly underneath the interface inducing the formation of strain-relieving misfit dislocations (MDs) during subsequent thermal annealing. Using H+ ion implantation, nearly complete strain relaxation of Si1−xGex layers with Ge fractions up to 22 at.% was obtained at temperatures as low as 800°C and the samples appeared free of threading dislocations (TDs) within the SiGe layer to the limit of transmission electron microscopy (TEM) analysis. Efficient strain relaxation was demonstrated even for Si1−xGex layers with Ge fractions up to 30 at.% using He+ ion implantation. We have thus developed a method for producing high-quality, thin, relaxed Si1−xGex films on Si(1 0 0) with TD densities well below 10 7 cm −2 by standard techniques as MBE and ion implantation. The heterostructures were analyzed using X-ray diffraction (XRD), Rutherford backscattering/channeling spectrometry and TEM. We propose a model of strain relaxation in which dislocations generated in conjunction with the formation of H or He filled overpressurized cavities glide to the interface where they form strain-relieving misfit segments. On the basis of this assumption, the conditions for efficient strain relaxation are discussed.

Bernhard Holländer

Papers

Measurement of the band offsets between amorphous LaAlO3 and silicon

Band engineering and growth of tensile strained Ge/(Si)GeSn heterostructures for tunnel field effect transistors

Strain relaxation mechanism for hydrogen-implanted Si1−xGex/Si(100) heterostructures

Direct Bandgap Group IV Epitaxy on Si for Laser Applications

Strain relaxation of pseudomorphic heterostructures after hydrogen or helium ion implantation for virtual substrate fabrication