An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the gate oxide film for high voltage formed in the cell region and the low voltage region by a predetermined depth, by forming photoresist patterns to expose the gate oxide film for high voltage formed in the cell region and the low voltage region, and performing a wet etching process using the photoresist patterns as an etching mask, removing the entire gate oxide film for high voltage formed in the cell region and the low voltage region, by performing a cleaning process on the resulting structure, removing the photoresist patterns, forming a floating gate electrode and a control gate electrode, by sequentially forming a tunnel oxide film, a first polysilicon film, a second polysilicon film, a dielectric film, a third polysilicon film and a metal silicide film on the whole surface of the resulting structure, and patterning the resulting structure, and forming source and drain regions, by implanting ions by using the gate electrodes as an ion implant mask.

Method of manufacturing flash memory device

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit

A method for fabricating a transistor device on a semiconductor substrate, comprising the following steps. A semiconductor substrate having a silicon surface with an overlying insulating dielectric layer is provided. The insulating dielectric layer is patterned to define hole/channel regions having predetermined widths. An amorphous silicon layer is formed having a predetermined thickness over the dielectric layer and the hole/channel regions, filling the hole/channel regions. Heating (grain growth) the amorphous silicon layer to form a planar silicon layer, comprising at least a portion of epitaxial-silicon, having a predetermined thickness, over the dielectric layer and through the hole/channel regions, filling the hole/channel regions. The planar silicon layer is patterned to expose the hole/channel regions and define transistor regions. Trenches are formed in the silicon surface adjacent the transistor regions. Shallow trench isolation regions are formed filling the trenches and having a predetermined depth. Transistor structures are formed within the transistor regions, separated by the shallow trench isolation regions.

Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors

A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.

CMOS output circuit with enhanced ESD protection using drain side implantation

A predictive, physically based substrate resistance model for CMOS transistors operating at radio frequencies (RF) is described. This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths.

Modeling and optimization of substrate resistance for RF-CMOS

The present invention provides a method of placing and routing metal wires for integrated circuit. In the method, a grid pattern is constructed by a plurality of floors with metal wires The grid size is set to be equal to a metal pitch. However, each via placed in the grid pattern has to be constrained by a checkerboard-like pattern. The checkerboard-like pattern consists of potential via sites and forbidden sites, wherein the potential via sites and the forbidden sites are intervened each other so that each potential via site in a comer of the grid has forbidden sites at its nearest neighbor corners. Furthermore, the connection cells is constructed and placed in a defined via site for connecting the metal wires in individually floor.

Place and route method for integrated circuit design

This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED.

https://ir.nctu.edu.tw:443/bitstream/11536/30092/1/000165684000018.pdf

Boon-Khim Liew

Papers

Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors

CMOS output circuit with enhanced ESD protection using drain side implantation

Modeling and optimization of substrate resistance for RF-CMOS

Place and route method for integrated circuit design

Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology