Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO 2 . Forming a layer of hafnium oxide by atomic layer deposition and forming a layer of a lanthanide oxide by electron beam evaporation, where the layer of hafnium oxide is adjacent and in contact with the layer of lanthanide, provides a dielectric layer with a relatively high dielectric constant as compared with silicon oxide. The dielectric can be formed as a nanolaminate of hafnium oxide and a lanthanide oxide.

Lanthanide oxide / hafnium oxide dielectric layers

A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the subsequent converting step includes oxidizing a metal atomic layer to form a metal oxide layer. The atomic layer deposition and oxidation step are then repeated to produce a metal oxide layer having sufficient thickness for use as a metal oxide layer in an integrated circuit. The subsequent converting step, in an embodiment, includes converting the atomic deposition layer by exposing it to one of nitrogen to form a nitride layer, carbon to form a carbide layer, boron to form a boride layer, and fluorine to form a fluoride layer. Systems and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method are also described.

Atomic layer deposition and conversion

Integrated circuits, the key components in thousands of electronic and computer products, are generally built layer by layer on a silicon substrate. One common technique for forming layers is called chemical-vapor deposition (CVD.) Conventional CVD systems not only form layers that have non-uniform thickness, but also have large chambers that make the CVD process wasteful and slow. Accordingly, the inventor devised new CVD systems, methods, and apparatuses. One exemplary CVD system includes an outer chamber, a substrate holder, and a unique gas-distribution fixture. The fixture includes a gas-distribution surface having holes for dispensing a gas and a gas-confinement member that engages or cooperates with the substrate holder to form an inner chamber within the outer chamber. The inner chamber has a smaller volume than the outer chamber, which not only facilitates depositions of more uniform thickness, but also saves gas and speeds up the deposition process.

Methods, systems, and apparatus for uniform chemical-vapor depositions

Electrical and reliability properties of ultrathin La/sub 2/O/sub 3/ gate dielectric have been investigated. The measured capacitance of 33 /spl Aring/ La/sub 2/O/sub 3/ gate dielectric is 7.2 /spl mu/F/cm/sup 2/ that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 /spl Aring/. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm/sup 2/ at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3/spl times/10/sup 10/ eV/sup -1//cm/sup 2/, and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO/sub 2/.

https://ir.nctu.edu.tw:443/bitstream/11536/30423/1/000087898300005.pdf

Electrical characteristics of high quality La 2 O 3 gate dielectric with equivalent oxide thickness of 5 /spl Aring/

The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric layer of cerium oxide and aluminum oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memory, or as a dielectric in an NROM device, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film.

Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics

High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ are fabricated with EOT of 4.8 and 9.6 /spl Aring/, leakage current of 0.06 and 0.4 A/cm/sup -2/ and D/sub it/ of both 3/spl times/10/sup 10/ eV/sup -1//cm/sup 2/, respectively. The high K is further evidenced from high MOSFET's I/sub d/ and g/sub m/ with low I/sub OFF/. Good SILC and Q/sub BD/ are obtained and comparable with SiO/sub 2/. The low EOT is due to the high thermodynamic stability in contact with Si and stable after H/sub 2/ annealing up to 550/spl deg/C.

https://ir.nctu.edu.tw:443/bitstream/11536/19275/1/000088359300006.pdf

High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ gate dielectrics with equivalent oxide thickness 5-10 /spl Aring/

We report a very simple process to fabricate Al/sub 2/O/sub 3/ gate dielectric for CMOS technology with k (9.0 to 9.8) greater than Si/sub 3/N/sub 4/. Al/sub 2/O/sub 3/ is formed by direct oxidation from thermally evaporated Al. The 48 /spl Aring/ Al/sub 2/O/sub 3/ has /spl sim/7 orders lower leakage current than equivalent 21 /spl Aring/ SiO/sub 2/. A good Al/sub 2/O/sub 3/-Si interface was evidenced by the low interface density of 1/spl times/10/sup 11/ eVcm/sup -2/ and compatible electron mobility with thermal SiO/sub 2/. Good reliability is measured from the small stress induced leakage current (SILC) after 2.5 V stress for 10,000 s.

Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/

For the first time, high density (10.3 fF//spl mu/m/sup 2/), low voltage linearity (/spl alpha/=89 ppm/V/sup 2/) and small leakage current (1.2/spl times/10/sup -82/ A/cm/sup 2/ or 5.8 fA/[pF/spl middot/V] at 2V) meet all the ITRS requirements of analog capacitor at year 2018. These are achieved by novel high-K TiTaO (K=45) and high work-function Ir capacitor, which further improve to very high 23 fF//spl mu/m/sup 2/ density and low 81 ppm/V/sup 2/ linearity for higher speed analog/RF ICs at 1GHz, using the fast /spl alpha/ decay mechanism with increasing frequency.

Very high K and high density TiTaO MIM capacitors for analog and RF applications

We demonstrate three-dimensional (3-D) self-aligned [IrO/sub 2/-IrO/sub 2/-Hf]-LaAlO/sub 3/-Ge-on-Insulator (GOI) CMOS FETs above 0.18-/spl mu/m Si CMOS FETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO/sub 2/-LaAlO/sub 3/-GOI p-MOSFETs and IrO/sub 2/-Hf-LaAlO/sub 3/-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm/sup 2//Vs respectively, without depredating the underneath 0.18-/spl mu/m Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.

https://ir.nctu.edu.tw:443/bitstream/11536/23667/1/000226479100023.pdf

Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

High-performance TaN/TiLaO/La2O3/SiO2/ (111)-Ge nMOSFETs show high mobility of 432 cm2/V ·s at 1013 cm-2 carrier density (Ns), good 1.05 junction ideality factor, and small subthreshold swing of 101 mV/dec, at a small 1.1-nm capacitance-equivalent thickness (CET). This is the first report of higher mobility in the Ge nMOSFET than SiO2/Si universal mobility at wide medium-high Ns range and small CET of 1.1 nm, which is attributed to using the (111)-Ge substrate, 30-ns laser annealing, SiO2 interfacial layer, and YbGex/n-Ge contact.

https://ir.nctu.edu.tw:443/bitstream/11536/21019/1/000314173200005.pdf

C.C. Liao

Papers

High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ gate dielectrics with equivalent oxide thickness 5-10 /spl Aring/

Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/

Very high K and high density TiTaO MIM capacitors for analog and RF applications

Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

Metal-Gate/High- $\kappa$ /Ge nMOS at Small CET With Higher Mobility Than $\hbox{SiO}_{2}/\hbox{Si}$ at Wide Range Carrier Densities