Showing papers by "Carl V. Thompson published in 2009"

Densely Packed Arrays of Ultra-High-Aspect-Ratio Silicon Nanowires Fabricated using Block-Copolymer Lithography and Metal-Assisted Etching

Abstract: Metal-assisted etching is used in conjunction with block-copolymer lithography to create ordered and densely-packed arrays of high-aspect-ratio single-crystal silicon nanowires with uniform crystallographic orientations. Nanowires with diameters and spacings down to 19 nm and 10 nm, respectively, are created as either continuous carpets or as carpets within trenches. Wires with aspect ratios up to 220 are fabricated, and capillary-induced clustering of wires is eliminated through post-etching critical point drying. The wires are single crystals with 〈100〉 axis directions. The distribution of wire diameters is narrow and closely follows the size distribution of the block copolymer, with a standard deviation of 3.12 nm for wires of mean diameters 22.06 nm. Wire arrays formed in carpets and in channels have hexagonal order with good fidelity to the block copolymer pattern. Fabrication of wires in topographic features demonstrates the ability to accurately control wire placement. Wire arrays made using this new process will have applications in the creation of arrays of photonic and sensing devices.

Low Temperature Synthesis of Vertically Aligned Carbon Nanotubes with Electrical Contact to Metallic Substrates Enabled by Thermal Decomposition of the Carbon Feedstock

Abstract: Growth of vertically aligned carbon nanotube (CNT) carpets on metallic substrates at low temperatures was achieved by controlled thermal treatment of ethylene and hydrogen at a temperature higher than the substrate temperature. High-resolution transmission electron microscopy showed that nanotubes were crystalline for a preheating temperature of 770 °C and a substrate temperature of 500 °C. Conductive atomic force microscopy measurements indicated electrical contact through the CNT carpet to the metallic substrate with an approximate resistance of 35 kΩ for multiwall carpets taller than two micrometers. An analysis of the activation energies indicated that thermal decomposition of the hydrocarbon/hydrogen gas mixture was the rate-limiting step for low-temperature chemical vapor deposition growth of CNTs. These results represent a significant advance toward the goal of replacing copper interconnects with nanotubes using CMOS-compatible processes.

Solid-state dewetting of patterned thin films

Abstract: Gold particle arrays have been produced through solid-state dewetting of patterned gold thin films. Patterns included rectangles and terminated lines of different widths, lengths, and film thickness. The particle spacing in long lines followed a Rayleigh-like dependence on the cross-sectional area of the line. Shorter lines had lower numbers of particles, indicating line-end effects. In some cases, ordered particle arrays were obtained. The probability of forming ordered particle arrays was shown to depend on the relative magnitudes of the length, width, and thickness of patterned structures. These trends are captured in design maps.

Cobalt Nanoparticle Arrays made by Templated Solid‐State Dewetting

Abstract: Self-assembled cobalt particle arrays are formed by annealing, which cause agglomeration (dewetting) of thin Co films on oxidized silicon substrates that are topographically prepatterned with an array of 200-nm-period pits. The Co nanoparticle size and uniformity are related to the initial film thickness, annealing temperature, and template geometry. One particle per 200-nm-period pit is formed from a 15-nm film annealed at 850 degrees C; on a smooth substrate, the same annealing process forms particles with an average interparticle distance of 200 nm. Laser annealing enables templated dewetting of 5-nm-thick films to give one particle per pit. Although the as-deposited films exhibit a mixture of hexagonal close-packed and face-centered cubic (fcc) phases, the ordered cobalt particles are predominantly twinned fcc crystals with weak magnetic anisotropy. Templated dewetting is shown to provide a method for forming arrays of nanoparticles with well-controlled sizes and positions.

Direct evidence for effects of grain structure on reversible compressive deposition stresses in polycrystalline gold films.

Abstract: A component of the compressive stress that develops during deposition of polycrystalline thin films reversibly changes during interruptions of growth. The mechanism responsible for this phenomenon has been the subject of much recent speculation and experimental work. In this Letter, we have varied the in-plane grain size of columnar polycrystalline gold films with a fixed thickness, by varying their thermal history. Without a vacuum break, the stress in these films was then measured in situ during growth and during interruptions in growth. Homoepitaxial gold films were similarly characterized as part of this study. The inverse of the in-plane grain size and the corresponding reversible stress change were found to be proportional, with zero reversible stress change observed for infinite grain size (homoepitaxial films). These results demonstrate a clear role of grain size in the reversible changes in gold films.

Experimental characterization and modeling of the contact resistance of Cu–Cu bonded interconnects

Abstract: The effects of the surface roughness and applied loads on the specific electrical contact resistance of three-dimensional Cu–Cu bonded interconnects have been quantitatively investigated. Wafer-level thermocompression bonding was carried out on bonded Cu layers with either different surface roughness at a certain load or with similar surface roughness at different applied loads. Experimental results show that as the surface roughness of the Cu bonding layer increases or as the bonding load decreases, the specific contact resistance of the bonded interconnects increases. A model is presented which quantifies the relationship between the specific contact resistance and the true contact area (which is a function of the surface roughness and applied load). Through the true contact area, the integrity of a bonded interface may be predicted from the electrical measurement of the contact resistance.

Catalyst proximity effects on the growth rate of Si nanowires

Abstract: Si nanowires grown by the vapor-liquid-solid (VLS) mechanism were fabricated using Au-catalyst nanoparticles and silane (SiH4) gas on Si substrates. Au was deposited on the substrate surface both by electron-beam evaporation and Au-colloid deposition. Both kinking defects and vertical nanowire epitaxy on Si ⟨111⟩ substrates were found to be directly related to SiH4 flow rate. A correlation between Au-colloid dilution and the nanowire growth rate was also observed, with the growth rate increasing with increasing concentrations of Au-catalyst particles on the wafer surface. Systematic experiments relating the nanowire growth rate to the proximity of nearest-neighbor Au particles and Au reservoirs were carried out, and the results were found to be in good agreement with a SiH4 reaction model, which associates decomposition to form SiH2 with higher nanowire growth rates. Implications toward the realization of VLS-grown single nanowire transistors are discussed.

Formation of single tiers of bridging silicon nanowires for transistor applications using vapor-liquid-solid growth from short silicon-on-insulator sidewalls.

Abstract: Single tiers of silicon nanowires that bridge the gap between the short sidewalls of silicon-on-insulator (SOI) source/drain pads are formed. The formation of a single tier of bridging nanowires is enabled by the attachment of a single tier of Au catalyst nanoparticles to short SOI sidewalls and the subsequent growth of epitaxial nanowires via the vapor-liquid-solid (VLS) process. The growth of unobstructed nanowire material occurs due to the attachment of catalyst nanoparticles on silicon surfaces and the removal of catalyst nanoparticles from the SOI-buried oxide (BOX). Three-terminal current-voltage measurements of the structure using the substrate as a planar backgate after VLS nanowire growth reveal transistor behaviour characteristics.

Electromigration-induced bond improvement for three-dimensional integrated circuits

Abstract: Bonded Cu interconnects were stressed with increasing current while the contact resistance was measured. Interconnects with high initial contact resistance exhibited a contact resistance reduction phenomenon at a critical current density. The higher the initial contact resistance is, the lower the current required to trigger this phenomenon. Interconnects with low initial contact resistances exhibit this phenomenon only when stressed at a higher temperature. Electromigration is shown to be the most likely mechanism responsible for this phenomenon. This behavior can be used for low-temperature improvement of the quality of bonded interconnects for three-dimensional integrated circuits.

Effect of bonding and aging temperatures on bond strengths of Cu with 75Sn25In solders

Abstract: In the present study, the interaction between thin film Cu and non-eutectic Sn-In is studied. The effects of the bonding and aging temperature on microstructure, IMC formation and also shear strength are investigated by SEM/EDX, XRD and shear testing. The bonding mechanism is proposed based on the obtained results. The bonding mechanism is proposed to occur over 2 stages: • An increase in bonding temperatures leads to an increase in the true contact area, and • The aging temperature leads to interdiffusion and assists formation of the IMC. The type of IMC that forms is η phase (Cu 6 (Sn,In) 5 ) which is similar to the interaction between Cu and eutectic Sn-In. The shear strength increases with increasing the bonding temperature. On the other hand, the aging temperature does not have a significant impact on the shear strength. This indicates that the shear strength is mostly affected by the true contact area rather than the IMC formation.

A Study on Morphology Control of ZnO Electrodeposited on Au Surface

Abstract: ZnO was electrodeposited on single-crystal, highly (111) textured polycrystalline, and randomly aligned polycrystalline Au films serving as the cathodes. The electrodeposition was carried out in a zinc nitrate aqueous solution at 65°C. The morphologies and crystal structures of ZnO were closely related to the properties of the Au surface. A detailed analysis was conducted, and the conclusion is that while the structural properties of ZnO can be controlled by controlling the crystal properties of Au film, the optical properties of ZnO are similar under the same electrodeposition conditions. However, using a two-step electrodeposition, smooth and compact epitaxial ZnO films are obtained.

Multilevel reservoirs for integrated circuit interconnects

Abstract: Embodiments of an on-chip interconnect having a multilevel reservoir are provided In general, the on-chip interconnect is an interconnect within an integrated circuit and includes an interconnect segment and a multilevel reservoir The interconnect segment has an anode end and a cathode end The multilevel reservoir is adjacent to the cathode end of the interconnect segment and operates as a reservoir of metal atoms As such, any electromigration-induced void begins forming in the multilevel reservoir rather than the cathode end of the interconnect segment As a result, a reliability of the on-chip interconnect is substantially improved as compared to that of traditional on-chip interconnects In addition, by utilizing multiple levels of the integrated circuit, a volume of the multilevel reservoir is substantially increased as compared to a volume of a corresponding single-level reservoir

Editorial Preface to the Special Section on Electromigration Published in March 2009

Abstract: , we published aSpecial Section containing papers on the topic of electromigra-tion in Cu interconnects. At the time of publication, we couldnot include a preface to the Special Section. This issue containsthe preface to provide a background to the meeting where thepapers were originally presented and the significance of thematerial contained in the papers.The Workshop on Electromigration Reliability was orga-nized as a companion workshop (workshop www.sispad.org/sispad/sispad-events/sispad-2007/companion-workshops.html)of the International Conference on Simulation of Semiconduc-tor Processes and Devices (www.sispad.org) which was hostedin2007inVienna,Austria,bytheInstituteforMicroelectronicsof TU Wien. The goal of the workshop was to present aprofound review and the newest expertise on electromigrationby invited talks of leading researchers.Electromigration is a complex multiphysics problem includ-ing electrical, thermal, and mechanical aspects, with a strongdependence on the microstructure of the interconnect metal.Metal grain boundaries are fast diffusivity paths and have a sig-nificant influence on the electromigration behavior. The choiceof surrounding layers, e.g., barrier and capping layer, has alsoa huge impact on the electromigration behavior. The atomicstructure of the interfacial region can enhance or suppresselectromigration. Design and material choice determine themechanical stress distribution as well as the thermal householdof an interconnect layout. Mechanical stress is an additionaldriving force for material transport and is also a source of elec-tromigration anisotropy. The interconnect process technologydetermines the properties of the metal microstructure and canalso introduce defects dramatically accelerating electromigra-tion degradation.The speakers at the workshop were Joseph J. Clement(Sandia National Laboratories, U.S.), Jeff Gambino (IBM,U.S.), Chee Lip Gan (Nanyang Technological University,Singapore), Alexander von Glasow (Infineon, Germany),Jim R. Lloyd (IBM, U.S.), Valeriy Sukharev (Ponte Solu-tions, U.S.), Carl V. Thompson (Massachusetts Institute ofTechnology, U.S.), King-Ning Tu (University of California atLosAngeles,U.S.),EhrenfriedZschech(AMD,Germany),andHajdinCeric(InstituteforMicroelectronics,TUWien,Austria).