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Chien-Chung Hung

Researcher at Industrial Technology Research Institute

Publications -  71
Citations -  879

Chien-Chung Hung is an academic researcher from Industrial Technology Research Institute. The author has contributed to research in topics: Magnetoresistive random-access memory & Layer (electronics). The author has an hindex of 16, co-authored 71 publications receiving 807 citations. Previous affiliations of Chien-Chung Hung include TSMC.

Papers
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Proceedings ArticleDOI

Racetrack memory cell array with integrated magnetic tunnel junction readout

TL;DR: In this article, the first demonstration of CMOS-integrated racetrack memory was reported, which is complete memory cells integrated into the back end of line of IBM 90 nm CMOS.
Patent

Structure and access method for magnetic memory cell and circuit of magnetic memory

TL;DR: A magnetic memory cell, used in a magnetic memory device, includes a stacked magnetic pinned layer, serving as a part of the base structure as discussed by the authors, between which there is a sufficient large magnetic coupling force to maintain magnetization of the top pinned layer on a reference direction.
Journal ArticleDOI

Reduction in critical current density for spin torque transfer switching with composite free layer

TL;DR: In this paper, a composite free layer (CFL) consisting of a soft layer and a hard layer exchange coupled in parallel is proposed to reduce the critical current density (Jc).
Proceedings ArticleDOI

High efficiency high reliability SiC MOSFET with monolithically integrated Schottky rectifier

TL;DR: A junction barrier controlled Schottky rectifier integrated silicon carbide MOSFET (SiC JMOS) was proposed in this paper, which merged a double implanted MOS FET (DMOS) and junction barrier control Schottkey diode (JBS) in a monolithic SiC device without any additional process and area penalty.
Patent

Multi-sensing level MRAM structures

TL;DR: In this paper, the authors presented an improved magnetic memory cell that includes a switching element and two magnetic tunnel junction (MTJ) devices in a parallel configuration, and serially connecting the parallel configuration to an electrode of the switching element.