C
Chris Paone
Researcher at University of Rochester
Publications - 4
Citations - 111
Chris Paone is an academic researcher from University of Rochester. The author has contributed to research in topics: Sense amplifier & eDRAM. The author has an hindex of 3, co-authored 3 publications receiving 109 citations.
Papers
More filters
Proceedings ArticleDOI
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS
Gregory J. Uhlmann,T. Aipperspach,Toshiaki Kirihata,K. Chandrasekharan,Yan Zun Li,Chris Paone,B. Reed,Norman Robson,John M. Safran,D. Schmitt,S.S. Iyer +10 more
TL;DR: A second-generation one-time programmable read-only memory (OTPROM) that provides these features through a balanced bitline, resistor pull-up, differential sense amp with a programmable reference is described.
Journal ArticleDOI
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
Gregory J. Fredeman,Donald W. Plass,Abraham Mathews,Janakiraman Viraraghavan,Kenneth J. Reyer,Thomas J. Knips,Thomas R. Miller,Elizabeth L. Gerhard,Dinesh Kannambadi,Chris Paone,Dongho Lee,Daniel J. Rainey,Michael A. Sperling,Michael Whalen,Steven Burns,Rajesh R. Tummuru,Herbert L. Ho,Alberto Cestero,Norbert Arnold,Babar A. Khan,Toshiaki Kirihata,Subramanian S. Iyer +21 more
TL;DR: A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm2 deep-trench capacitor cell that enables a high voltage gain of a power-gated inverter at mid-level input voltage.
Proceedings ArticleDOI
17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access
Gregory J. Fredeman,Donald W. Plass,Abraham Mathews,Kenneth J. Reyer,Thomas J. Knips,Thomas R. Miller,Elizabeth L. Gerhard,Dinesh Kannambadi,Chris Paone,Dongho Lee,Daniel J. Rainey,Michael A. Sperling,Michael Whalen,S. Burns +13 more
TL;DR: This 22nm design style has been migrated into a 14nm FinFET learning vehicle, complete with an ABIST engine, wordline charge pumps (VPP and VWL), and padcage interface circuitry.
Proceedings ArticleDOI
Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs
TL;DR: In this article , scaling trends in the alpha-particle and neutron induced SRAM SER shows an increase in the per-bit SER and percent multi-cell upsets at the 5-nm FinFET process compared to the 7-nm process.