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Christopher Clarke

Researcher at Lancaster University

Publications -  79
Citations -  967

Christopher Clarke is an academic researcher from Lancaster University. The author has contributed to research in topics: Field-programmable gate array & Eye tracking. The author has an hindex of 15, co-authored 75 publications receiving 761 citations. Previous affiliations of Christopher Clarke include University of Bath & Nanyang Technological University.

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Journal ArticleDOI

Design and validation of a LED-based high intensity photocatalytic reactor for quantifying activity measurements

TL;DR: In this article, the authors describe the design of a novel standardized reactor for accurate measurements of the efficiency of photocatalytic materials under well-controlled lighting conditions, and demonstrate that for many of the configurations and distances examined a poor homogeneity over the catalyst surface is obtained if the LED configuration is not carefully designed.
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Very Low-Noise ENG Amplifier System Using CMOS Technology

TL;DR: This device, which is an extension of the conventional nerve signal recording cuff, enables ENG to be classified by action potential velocity and provides preliminary in vitro data obtained from frogs that demonstrate the validity of the technique for the first time.
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Motion Correlation: Selecting Objects by Matching Their Movement

TL;DR: Motion correlation has been explored in earlier work but only recently begun to feature in holistic interface designs as discussed by the authors, where users are guided by motion feedback, and only need to copy a presented motion.
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Nonlinear dynamics of a bistable piezoelectric-composite energy harvester for broadband application

TL;DR: In this paper, an arrangement of piezoelectric layers attached to a bistable asymmetric laminate is investigated experimentally to understand the dynamic response of the structure and power generation characteristics.
Proceedings ArticleDOI

A reverse converter for the 4-moduli superset {2/sup n/-1, 2/sup n/, 2/sup n/+1, 2/sup n+1/+1}

TL;DR: To implement VLSI efficient modulo reduction, the authors propose two techniques-multiple split tables (MST) and a modified division algorithm (MDA).