Showing papers by "Cicero S. Vaucher published in 2003"

A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-/spl mu/m CMOS

Abstract: A low-power fully integrated synthesizer for Bluetooth applications is presented. The circuit with quadrature output signals at 2.45 GHz and 15-mW power dissipation has been designed in a digital 0.18-/spl mu/m CMOS process with 1.8-V supply voltage. The only external component is a 64-MHz crystal. Measurements have been performed on packaged samples mounted on an FR-4 board and show that the Bluetooth requirements are met. The measured phase noise is below -120 dBc/Hz at 3-MHz offset, and the resulting residual frequency modulation is 7.4-kHz rms. The tuning range consists of an analog and digital tuning mechanism, resulting in more than 15% overall tuning range.

Phase-locked-loop with reduced clock jitter

Abstract: The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology

Abstract: A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

Phase locked loop

Abstract: A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).

Multi-tap coil

Abstract: The invention relates to multi-band resonator circuits with inductors and capacitors. These resonator circuits are realized on integrated circuits. The inductors are realized according to the invention within one single coil comprising a center (2) tap and intermediate taps (4, 6).

A high frequency tuner

Abstract: A tuner for receiving a satellite broadcast signal via an antenna means, said tuner being coupled to a control unit. The tuner is characterized in that it comprises a standard bilateral digital interface for transmitting a base-band signal obtained from the received signal received via the antenna means and for receiving control signals transmitted by the control unit, said signals being transmitted/received via a first bilateral bus.

High frequency tuner

Abstract: A tuner for receiving a satellite broadcast signal via an antenna means, said tuner being coupled to a control unit. The tuner is characterized in that it comprises a standard bilateral digital interface for transmitting a base-band signal obtained from the received signal received via the antenna means and for receiving control signals transmitted by the control unit, said signals being transmitted/received via a first bilateral bus.

Head end having a low noise converter with channel preselecting frequency multiplexor

Abstract: A head end (7) comprises a low noise converter (2) for providing signal bands including channels to one or more user units (3). The low noise converter is arranged as a low noise channel converter (2), which includes frequency multiplexing means (6) for multiplexing one or more user pre-selected channels to the user units (3). By effecting pre-selection in the low noise channel converter (2) the connection between the head end (7) and the user units (3) only contains a single communication medium (5), generally an already installed coaxial cable (5). Wanted channels for example for watching one television program and simultaneously recording another program are pre-selected and at the side of the low noise block put on the one cable.

A Low-jitter 2.5-to-10 GHz Clock Multiplier Unit in CMOS

Abstract: — This paper demonstrates a low-jitter clock multiplier unit [1] that generates a 10 GHz output clock from a 2.5 GHz reference clock. An integrated 10 GHz LCoscillator is locked to the input clock, using a simple and fast phase detector circuit. This phase detector overcomes the speed limitation of a conventional tri-state Phase Frequency Detector, by eliminating an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18¹m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8 V supply.