New carrier mobility data for both arsenic- and boron-doped silicon are presented in the high doping range. The data definitely show that the electron mobility in As-doped silicon is significantly lower than in P-doped silicon for carrier concentrations higher than 1019cm-3. By integrating these data with those previously published, empirical relationships able to model the carrier mobility against carrier concentration in the whole experimental range examined to date (about eight decades in concentration) for As-, P-, and B-doped silicon are derived. Different parameters in the expression for the n-type dopants provide differentiation between the electron mobility in As-and in P-doped silicon. Finally, it is shown that these new expressions, once implemented in the SUPREM II process simulator, lead to reduced errors in the simulation of the sheet resistance values.

Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon

ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

The modeling, characterization, and design of monolithic inductors for silicon RF IC's

Ultra-thin MoS2 has recently emerged as a promising two-dimensional semiconductor for electronic and optoelectronic applications. Here, we report high mobility (>60 cm2/Vs at room temperature) field-effect transistors that employ unencapsulated single-layer MoS2 on oxidized Si wafers with a low level of extrinsic contamination. While charge transport in the sub-threshold regime is consistent with a variable range hopping model, monotonically decreasing field-effect mobility with increasing temperature suggests band-like transport in the linear regime. At temperatures below 100 K, temperature-independent mobility is limited by Coulomb scattering, whereas, at temperatures above 100 K, phonon-limited mobility decreases as a power law with increasing temperature.

Band-like transport in high mobility unencapsulated single-layer MoS 2 transistors

A Caughey–Thomas-like mobility model with temperature and composition dependent coefficients is used in this work to describe the dependence of electron and hole mobilities on temperature, doping concentration, and alloy composition. Appropriate parameter sets are given for a large number of III–V binary and ternary compounds, including: GaAs, InP, InAs, AlAs, GaP, Al0.3Ga0.7As, In0.52Al0.48As, In0.53Ga0.47As, and In0.49Ga0.51P. Additionally, physically justifiable interpolation schemes are suggested to find the mobilities of various ternary and quaternary compounds (such as AlxGa1−xAs, In1−xGaxP, In1−xGaxAs, In1−xAlxAs, and In1−xGaxAsyP1−y) in the entire range of composition. The models are compared with numerous measured Hall data in the literature and very good agreement is observed. The limitations of the present model are also discussed. The results of this work should be extremely useful in device simulation packages, which are currently lacking a reliable mobility model for the above materials.

Empirical low-field mobility model for III-V compounds applicable in device simulation codes

An analytical expression has been derived for the electron and hole mobility in silicon based on both experimental data and modified Brooks-Herring theory of mobility. The resulting expression allows one to obtain electron and hole mobility as a function of concentration up to \sim 10^{20} cm-3in an extended and continuous temperature range (250-500 K) within ± 13 percent of the reported experimental values.

Electron and hole mobilities in silicon as a function of concentration and temperature

The results of minority-carrier lifetime measurements in heavily phosphorus-doped n+diffused layers of p-n junction diodes using a spectral response technique are reported in this paper. Exact modeling of current-flow equations, modified to include bandgap reduction due to high carrier concentration and Auger recombination, is used to compute the dependence of diffused-layer photocurrent J pth on the incident light energy and intensity. The photocurrent in the diffused layer is also obtained by subtracting the theoretical value of the space charge and uniformly doped p-region component from the experimentally measured photocurrent of the diode at each wavelength. Note that all calculated values based on light intensity include computed transmittance/reflectance through the oxide layer at each wavelength. The comparison of the values of J pth with J pexp , using nonlinear least square techniques, then directly gives the lifetime profile in the diffused layer. A simple expression is given for lifetime as a function of doping which may be used in modeling and prediction of device performance. Using this experimental technique it was found that the lifetime in the diffused layer is an order of magnitude less than that corresponding to uniformly doped bulk-silicon values and is very much process dependent; its value being 3.72 × 10-11s for surface concentration of 3.0 × 1020cm-3and increases to 2.9 × 10-8s at doping concentration of 1.0 × 1017cm-3.

Modeling and measurement of minority-carrier lifetime versus doping in diffused layers of n + -p silicon diodes

This paper presents a unified theory for current transport in the monocrystalline emitter, thin oxide layer, and polycrystalline region of a bipolar transistor with a polysilicon emitter. The transport and tunneling equations are arranged in such a way that fast numerical solutions are readily obtained. A clear qualitative description is presented of the processes involved in gain determination and quantitative results are given for typical structures with various interfacial oxide layer thickness as a function of bias conditions.

The role of the interfacial layer in polysilicon emitter bipolar transistors

An approximate two-dimensional numerical analysis has been developed for studying double- (or triple-) diffused transistors. The program supplies dc and hf terminal characteristics (e.g., h fe , r bb , f T , I B , V BE ) over a wide range of operating collector currents and voltages for a given set of physical device parameters (mask dimensions, impurity profile, etc.). The approach is based on obtaining a set of differential equations describing current flow in the longitudinal (emitter-collector) direction and a separate differential equation describing current flow in the lateral direction. The assumption is made of space-charge or space-charge-neutral regions with current- and voltage-dependent boundaries. The equations are valid for arbitrary injection levels and automatically include such high-level effects as conductivity modulation, base widening, and emitter current crowding. Both theoretical and experimental results are given for transistors with f T values between 100 MHz and 3 GHz. The validity of the approach is confirmed and some areas requiring further study are outlined. The technique described is felt to be particularly attractive for the design and optimization of high-power microwave devices, due to the small computer execution time and memory requirements.

Simplified computer-aided analysis of double-diffused transistors including two-dimensional high-level effects

An experimental technique for determining the minority carrier diffusion length in the base region of Si p‐n junction diodes and solar cells is described. The procedure is to operate the device in the photoconductive mode and to measure its photoresponse in the wavelength region near the energy gap. The ratio of incident light intensity to photocurrent is a linear function of reciprocal absorption coefficient for each wavelength; the slope of the set of points directly yields the diffusion length. In addition, a nonlinear least‐squares analysis is also used to determine the diffusion length.

D.J. Roulston

Papers

Electron and hole mobilities in silicon as a function of concentration and temperature

Modeling and measurement of minority-carrier lifetime versus doping in diffused layers of n + -p silicon diodes

The role of the interfacial layer in polysilicon emitter bipolar transistors

Simplified computer-aided analysis of double-diffused transistors including two-dimensional high-level effects

Diffusion length determination in p‐n junction diodes and solar cells