Showing papers by "David Esseni published in 2012"

Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

Abstract: This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band k p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of Ion with a small degradation of the subthreshold slope, as well as large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values. Hence, an important widening of the range of Ioff and VDD values where tunnel FETs can compete with strained silicon MOSFETs is obtained.

Impact of interface traps on the IV curves of InAs Tunnel-FETs and MOSFETs: A full quantum study

Abstract: We present the first computational study employing a full quantum transport model to investigate the effect of interface traps in nanowire InAs Tunnel FETs and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on the NEGF formalism and on a 8×8 k·p Hamiltonian and accounting for phonon scattering. Our results show that: (a) even a single trap can detereorate the inverse sub-threshold slope (SS) of a nanowire InAs Tunnel FET; (b) the inelastic phonon assisted tunneling (PAT) through interface traps results in a temperature dependence of the Tunnel FETs IV characteristics; (c) the impact of interface traps on I off is larger in Tunnel FETs than in MOSFETs; (d) interface traps represent a sizable source of device variability.

Surface-Roughness-Induced Variability in Nanowire InAs Tunnel FETs

Abstract: We present a comparative study of the surfaceroughness (SR)-induced variability at low supply voltage VDD = 0.3 V in nanowire InAs tunnel FETs and strained-silicon (sSi) MOSFETs. By exploiting a 3-D full-quantum approach based on the Non-Equilibrium Green's Function formalism, we show that the Ion variability in InAs tunnel FETs is much smaller than the Ioff variability, whereas for VDD = 0.3 V, the sSi MOSFETs working in the subthreshold regime present similar Ion and Ioff variability. We explain the smaller Ion compared with Ioff variability of InAs tunnel FETs by noting that in the source depletion region, where tunneling mainly occurs for VGS = VDD, microscopic subband fluctuations induced by SR are small compared to macroscopic band bending due to the built-in potential of the source junction and to the gate bias. This results in SR-induced variability that is larger in InAs tunnel FETs than in sSi MOSFETs.

Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks

Abstract: In this paper, a novel technique to reduce the leakage current of FinFET forced stacks under a given delay constraint is presented. This technique takes advantage of the unique feature of four-terminal FinFETs allowing different transistors to have separately tunable back bias voltages. In this work, a reverse back bias voltage is applied to one of the two stacked transistors to reduce its leakage at the cost of a delay penalty, whereas a forward back bias voltage is applied to the other one to compensate this delay degradation. The technique is assessed by means of mixed device-circuit simulations for FinFETs that are representative of 40- and 27-nm technology generations. Results show that a leakage reduction by up to 50× can be achieved as compared with traditional transistor stacks, while keeping same speed, dynamic energy, and sensitivity to process/voltage/temperature variations.

Applicability of Macroscopic Transport Models to Decananometer MOSFETs

Abstract: We perform a comparative study of various macroscopic transport models against multisubband Monte Carlo (MC) device simulations for decananometer MOSFETs in an ultra-thin body double-gate realization. The transport parameters of the macroscopic models are taken from homogeneous subband MC simulations, thereby implicitly taking surface roughness and quantization effects into account. Our results demonstrate that the drift-diffusion (DD) model predicts accurate drain currents down to channel lengths of about 40 nm but fails to predict the transit frequency below 80 nm. The energy-transport (ET) model, on the other hand, gives good drain currents and transit frequencies down to 80 nm, whereas below 80 nm, the error rapidly increases. The six moments model follows the results of MC simulations down to 30 nm and outperforms the DD and the ET models.

Comparison Between Pseudospectral and Discrete Geometric Methods for Modeling Quantization Effects in Nanoscale Electron Devices

Abstract: This paper aims at comparing the pseudospectral method and discrete geometric approach for modeling quantization effects in nanoscale devices. To this purpose, we implemented a simulation tool, based on both methods, to solve a self-consistent Schrodinger-Poisson coupled problem for a 2-D electron carrier confinement according to the effective mass approximation model (suitable for FinFETs and nanowire FETs).

An improved procedure to extract the limiting carrier velocity in ultra scaled CMOS devices

Abstract: The validity of a previously published extraction technique for the limiting carrier velocity responsible for current saturation in nano-MOSFETs is carefully re-examined by means of accurate Multi Subband Monte Carlo transport simulations. By comparing the extracted limiting velocity to the calculated injection velocity, we identify the main sources of error of the extraction method. Then, we propose a new extraction procedure and extensively validate it. Our simulations and experimental results reconcile the values and trends of the extracted limiting velocity with the expectations stemming from quasi ballistic transport theory.

A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs

Abstract: This paper reports a simulation study investigating the drive current in the prototypical SiGe n-type FinFET depicted in Fig.1 and for different values of the Ge content x in the Si (1-x) Ge x active layer. To this purpose we performed strain simulations, band-structure calculations and Multi-Subband Monte Carlo transport simulations accounting for the effects of the Ge content on both the band-structure and scattering rates in the transistor channel. Our results suggest that the largest on-current may be obtained with a simple Si active layer.

Investigation of localized versus uniform strain as a performance booster in InAs Tunnel-FETs

Abstract: This paper investigates the effect of spatially localized versus uniform strain on the performance of n-type InAs nanowire Tunnel FETs. To this purpose we make use of a simulator based on the NEGF formalism and employing an eight-band k·p Hamiltonian, describing the strain implicitly as a modification of the band-structure. Our results indicate that, when the uniform strain degrades the subthreshold slope because of an increased band-to-band-tunneling at the drain, a localized strain at the source side can achieve a better tradeoff between on-current and subthreshold slope than a uniform strain configuration.