Power consumption is forecast by the International Technology Roadmap of Semiconductors (ITRS) to pose long-term technical challenges for the semiconductor industry. The purpose of this paper is threefold: (1) to provide an overview of strategies for powering MEMS via non-regenerative and regenerative power supplies; (2) to review the fundamentals of piezoelectric energy harvesting, along with recent advancements, and (3) to discuss future trends and applications for piezoelectric energy harvesting technology. The paper concludes with a discussion of research needs that are critical for the enhancement of piezoelectric energy harvesting devices.

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Powering MEMS portable devices—a review of non-regenerative and regenerative power supply systems with special emphasis on piezoelectric energy harvesting systems

Organic (opto)electronic materials have received considerable attention due to their applications in thin-film-transistors, light-emitting diodes, solar cells, sensors, photorefractive devices, and many others. The technological promises include low cost of these materials and the possibility of their room-temperature deposition from solution on large-area and/or flexible substrates. The article reviews the current understanding of the physical mechanisms that determine the (opto)electronic properties of high-performance organic materials. The focus of the review is on photoinduced processes and on electronic properties important for optoelectronic applications relying on charge carrier photogeneration. Additionally, it highlights the capabilities of various experimental techniques for characterization of these materials, summarizes top-of-the-line device performance, and outlines recent trends in the further development of the field. The properties of materials based both on small molecules and on conjug...

Organic Optoelectronic Materials: Mechanisms and Applications

Soleil et peau

IEEE International Solid-State Circuits Conference

A high-mobility organic semiconductor employed as the active material in a field-effect transistor does not guarantee per se that expectations of high performance are fulfilled. This is even truer if a downscaled, short channel is adopted. Only if contacts are able to provide the device with as much charge as it needs, with a negligible voltage drop across them, then high expectations can turn into high performances. It is a fact that this is not always the case in the field of organic electronics. In this review, we aim to offer a comprehensive overview on the subject of current injection in organic thin film transistors: physical principles concerning energy level (mis)alignment at interfaces, models describing charge injection, technologies for interface tuning, and techniques for characterizing devices. Finally, a survey of the most recent accomplishments in the field is given. Principles are described in general, but the technologies and survey emphasis is on solution processed transistors, because it is our opinion that scalable, roll-to-roll printing processing is one, if not the brightest, possible scenario for the future of organic electronics. With the exception of electrolyte-gated organic transistors, where impressively low width normalized resistances were reported (in the range of 10 Ω·cm), to date the lowest values reported for devices where the semiconductor is solution-processed and where the most common architectures are adopted, are ∼10 kΩ·cm for transistors with a field effect mobility in the 0.1-1 cm(2)/Vs range. Although these values represent the best case, they still pose a severe limitation for downscaling the channel lengths below a few micrometers, necessary for increasing the device switching speed. Moreover, techniques to lower contact resistances have been often developed on a case-by-case basis, depending on the materials, architecture and processing techniques. The lack of a standard strategy has hampered the progress of the field for a long time. Only recently, as the understanding of the rather complex physical processes at the metal/semiconductor interfaces has improved, more general approaches, with a validity that extends to several materials, are being proposed and successfully tested in the literature. Only a combined scientific and technological effort, on the one side to fully understand contact phenomena and on the other to completely master the tailoring of interfaces, will enable the development of advanced organic electronics applications and their widespread adoption in low-cost, large-area printed circuits.

Charge injection in solution-processed organic field-effect transistors: physics, models and characterization methods.

A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed simulations and analytical modelling of the potential and electron/hole concentrations. The enhancement of the interface coupling effect in ultra thin body devices, called super-coupling, can explain previously published experimental data [Pretet J, Ohata A, Dieudonne F, Allibert F, Bresson N, Matsumoto T, et al. Scaling issues for advanced SOI devices: gate oxide tunneling, thin buried oxide, and ultra-thin films. In: 7th International symposium silicon nitride and silicon dioxide thin insulating films, Paris, France, 2003. Electrochemical Society Proceedings, vol. 2003-02, Pennington (USA); 2003. p. 476–87], and reveals new challenges in the characterization of advanced SOI devices.

Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t Si, and the gate oxide thickness t OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple threshold voltage model of an undoped symmetrical double-gate MOSFET has been developed, based on an analytical solution of Poisson's equation for the potential distribution. The model has been verified by comparing the threshold voltage roll-off with the channel length with simulation results for different silicon thicknesses, gate oxide thicknesses, and drain voltage values. Good agreement between model and simulation results is obtained by calibrating the minimum carrier charge sheet density adequate to achieve the turn-on condition.

Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs

We report on the high-field (up to 10T) magnetoresistance measurements performed on the short (down to 75-nm gate length) n-type Si metal-oxide-semiconductor field-effect transistors. The electron magnetoresistance mobility of these nanometer devices was determined for a wide range of the electron concentration (107–1013cm−2, i.e., from a weak to a strong inversion) and gate length (10μm–75nm). In the case of long samples, the magnetoresistance mobility was compared to the effective mobility obtained by the standard parameter extraction and the split C–V techniques. The results are discussed in terms of the scattering power-law two-dimensional transport analysis. The data clearly indicate a significant decrease of the mobility with the gate length reduction below 100nm.

Magnetoresistance characterization of nanometer Si metal-oxide-semiconductor transistors

The physical bases of the most commonly used methods for the one-dimensional calculation of direct-tunneling current in metal–oxide–semiconductor (MOS) structures (i.e., Bardeen’s approach, the resonant transfer matrix method, and transparency-based approximations) are discussed. Each of them is presented in detail, underlining in a simple way the basic principles. In particular, an original derivation for Bardeen’s approach is proposed. A comparison of the different methods is then carried out for the simple case of two square quantum wells, where analytical solutions can be given, and for actual MOS structures, taking into account quantization effects. It is shown that all these methods, despite the very different formalisms, are based on similar physical approaches and provide very close results.

Raphael Clerc

Papers

Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs

Magnetoresistance characterization of nanometer Si metal-oxide-semiconductor transistors

Theory of direct tunneling current in metal–oxide–semiconductor structures