D
David Esseni
Researcher at University of Udine
Publications - 296
Citations - 6533
David Esseni is an academic researcher from University of Udine. The author has contributed to research in topics: MOSFET & Electron mobility. The author has an hindex of 41, co-authored 278 publications receiving 5888 citations. Previous affiliations of David Esseni include University of Bologna & Bell Labs.
Papers
More filters
Book ChapterDOI
Chapter 9 – Device Modeling
TL;DR: In this article, the authors describe the modeling approaches developed for the simulation of germanium devices and the main focus is on metal-insulator-semiconductor (MIS) devices.
Journal ArticleDOI
Analytical Procedure for the Extraction of Material Parameters in Antiferroelectric ZrO2
Mattia Segatto,David Esseni +1 more
TL;DR: In this article , an analytical procedure to extract the anisotropy constants of antiferroelectric (AFE) materials from a few key features of the experimental polarization versus field curves is presented.
Proceedings ArticleDOI
Investigation of localized versus uniform strain as a performance booster in InAs Tunnel-FETs
TL;DR: In this paper, the effect of spatially localized versus uniform strain on the performance of n-type InAs tunnel FETs was investigated using a simulator based on the NEGF formalism and employing an eight-band k·p Hamiltonian.
Journal ArticleDOI
BipFLASH : A novel non-volatile memory cell concept for high-speed, low-power applications
David Esseni,Luca Selmi +1 more
TL;DR: A novel non-volatile memory cell architecture is presented, which remarkably improves injection efficiency over conventional channel hot electron programming and it is shown how this superior performance can be traded to achieve either low voltage-low power or high-speed operation.
Journal ArticleDOI
On the interpretation of MOS impedance data in both series and parallel circuit topologies
Enrico Caruso,Enrico Caruso,Jun Lin,Scott Monaghan,Karim Cherkaoui,Liam Floyd,Farzan Gity,Pierpaolo Palestri,David Esseni,Luca Selmi,Paul K. Hurley +10 more
TL;DR: In this article, the authors investigated the interplay between the series and parallel equivalent circuit representations of the MOS system conductance (G) and capacitance (C) in inversion.