There is a significant recent advance in filtering of the salt-and-pepper noise for digital images. However, almost all recent schemes for filtering of this type of noise are not taking into an account the shape of objects (in particular edges) in images. We have applied the block-matching and 3D filtering (BM3D) scheme in order to refine the output of the decision-based/adaptive median techniques. Obtained results are excellent, surpassing current state-of-the-art for about 2 dB for both grayscale and color images.

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BM3D filter in salt-and-pepper noise removal

This article presents a Gm-C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted Gm linearization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input Gm. This enables the input Gm to process the quantization noise, thereby improving the input range and linearity of the Gm-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional–integral (PI) transfer function is employed at the first integrator, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 $\mu \text{W}$ with a signal bandwidth of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment.

A 6.5- μ W 10-kHz BW 80.4-dB SNDR G m -C-Based CT ∆∑ Modulator With a Feedback-Assisted G m Linearization for Artifact-Tolerant Neural Recording

This paper presents an ultra-low-voltage high-performance bulk-input pseudo-differential operational transconductance amplifier for low-frequency applications. The proposed amplifier is designed using standard 65-nm CMOS technology and powered from 0.3-V supply with a stand by current consumption of 170-nA. Post-layout simulations with a load capacitance of 5 pF have been performed to validate the performance of the proposed amplifier. The proposed amplifier exhibits a DC gain of 60 dB and a phase margin of 53
 $$^\circ $$
 at unity gain frequency of 70 kHz for a load of 5 pF. The proposed OTA has shown improvement of five times and more than 2.5 times in small-signal and large-signal performance, respectively, when compared to the state of the art. In addition, the proposed transconductance amplifier is used to design a tunable second-order $$G_m{\text {-}}C$$
 low-pass filter. Simulation results show that tunable cutoff frequency is varying from 4 to 190 kHz which is obtained by varying the input-stage bias current from 1 to 200 nA.

A 0.3-V Pseudo-Differential Bulk-Input OTA for Low-Frequency Applications

An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (VCM) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is $45~\mu \text{W}$ when operated at 1 V power supply.

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A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

A 0.4 V, body-driven, fully differential, tail-less OTA based on current push-pull

This brief presents a technique to improve the power efficiency of an active- RC 1-bit continuous-time Delta-Sigma modulator (DSM). A passive- RC low-pass filter (LPF) is used in feedback after the 1-bit digital-to-analog converter (DAC). The LPF smooths out the rail-to-rail sharp edges of the DAC output to reduce the signal-swing and slew-rate requirements of the first amplifier in DSM. The LPF is also utilized to contribute a pole to the loop response of the modulator. It does not require a compensation filter and reduces the order of the active part of the loop filter. A third-order DSM was designed in a 0.18- ${\mu }\text{m}$ CMOS process. Measurement results show that it can achieve 79.1-dB SNDR over 100-kHz bandwidth while consuming only 59.1 ${\mu }\text{W}$ .

Improving Power Efficiency for Active- RC Delta-Sigma Modulators Using a Passive- RC Low-Pass Filter in the Feedback

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8---32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.

A 0.5-V low power analog front-end for heart-rate detector

Traditionally, a transconductor-C (Gm-C)-based delta sigma modulator (DSM) has its performance limited by the nonlinearity of its Gm circuits. To achieve sufficient linearity, source degeneration is typically applied to a Gm circuit, which inevitably reduces the Gm circuit’s transconductance and thermal noise efficiencies. This paper presents new ways to change this paradigm. First, a DSM topology that has a passive RC lowpass filter (LPF) in its feedback is applied. We place the cutoff frequency of the LPF at the signal band edge to realize a pole of the DSM’s loop filter, thus reducing the power consumption. The LPF also suppresses the high-frequency components of quantization noise, enabling us to use a nonlinear Gm circuit in the DSM’s feedback while not causing quantization noise to fold into the signal band. With matched transfer characteristics and inputs, the input and feedback Gm circuits have their nonlinearities canceled with each other. Second, a merged input-feedback Gm circuit with shared degeneration resistors is proposed, which has high transconductance and noise efficiencies and simultaneously allows large input and feedback signals. A prototype DSM fabricated in a 0.18- $\mu \text{m}$ CMOS process demonstrates the nonlinearity cancellation and power efficiency of the proposed methods.

A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement

A highly linear multi-level switched-capacitor (SC) digital-to-analog converter (DAC) is proposed for continuous-time delta-sigma modulators (CTDSMs). A Gm-C CTDSM with a passive frontend low-pass filter (LPF) is further proposed to mitigate the problems of increased settling requirements and worsened anti-aliasing capability (consequences of an SC DAC) so as to realize an extremely power-efficient CTDSM. A 100-kHz bandwidth $40\times $ oversampling 3rd-order CTDSM prototype employing the proposed DAC and modulator topology is fabricated in a low-leakage 65-nm CMOS technology. Experimental results show that the modulator achieves a spurious-free dynamic range (SFDR), dynamic range (DR) and signal-to-noise and distortion ratio (SNDR) of 86.6 dB, 85.1 dB and 78.8 dB, respectively. To the best of our knowledge, this is the first silicon-proven CTDSM with a more-than-3-level DAC that leads to an excellent SFDR while not requiring dynamic element matching, component calibration, precise reference voltages, or an operating frequency higher than the modulator’s sampling frequency ${{f}}_{{{s}}}$ . The prototype consumes 22.8 $\mu \text{W}$ from a 1.2-V supply, amounting to a Walden’s and Schreier’s figure of merit (FoM) of 16 fJ/conv.-step and 181.5 dB, respectively, which is the best among state-of-the-art CTDSMs. It further achieves high alias rejections of 52 dB and 58 dB at ${{f}}_{{{s}}}$ and $2{{f}}_{{{s}}}$ , respectively, and can tolerate a clock period jitter of 3 ns.

A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator

The development of deep-submicron CMOS IC fabrication technologies has brought portable, battery operated devices such as cardiac pacemakers and personal heart rate detectors to the market. This paper presents a 1.8 V analog front-end for heart-rate detector. The front-end includes cascaded preamplifier and filter designed to reduce the device flicker noise at ECG bandwidth. The sensed low amplitude ECG signal from a noisy environment is amplified by the preamplifier. Special feedback mechanism has been employed to increase the SNR against body-electrode source noise. The designed preamplifier is reported to achieve a SFDR (Spurious free dynamic range) of 87.5 dB with a total power consumption of 0.354 mW combined with the filter. The current design is carried out using BSIM3V3.2 model at 0.18 μm UMC process technology.

Debajit Basak

Papers

Improving Power Efficiency for Active- RC Delta-Sigma Modulators Using a Passive- RC Low-Pass Filter in the Feedback

A 0.5-V low power analog front-end for heart-rate detector

A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement

A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator

A low noise preamplifier and switched capacitor filter for heart-rate detection