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Deepak Mishra

Researcher at Indian Space Research Organisation

Publications -  19
Citations -  45

Deepak Mishra is an academic researcher from Indian Space Research Organisation. The author has contributed to research in topics: Turbo code & Error detection and correction. The author has an hindex of 3, co-authored 17 publications receiving 19 citations.

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Proceedings ArticleDOI

FPGA Implementation of FEC Encoder with BCH & LDPC Codes for DVB S2 System

TL;DR: The design and implementation of Xilinx FPGA based Forward Error Correction encoder for DVB S2 system which includes BCH code followed by LDPC code and finally bit mapped to constellation for QPSK modulation is given.
Journal ArticleDOI

Performance Analysis of Reliability-Based Decoding Algorithm for Short Block Length Turbo Codes

TL;DR: Demand for transmission using short block length messages has been increased recently in applications including satellite communication, mobile communication, wireless sensor networks, and machine ...
Book ChapterDOI

Design and Analysis of a Secure Coded Communication System Using Chaotic Encryption and Turbo Product Code Decoder

TL;DR: In this article, the design and analysis of a secure and reliable communication system accomplished using logistic map-based chaotic encryption and turbo product codes is presented. But the system is simulated using MATLAB and it is shown that the use of encryption for secure communication does not degrade the system performance.
Journal ArticleDOI

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study.

TL;DR: The implementation results show that there is barely any change in the LUTs used and power dissipation due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan.
Proceedings ArticleDOI

Low Power and Area Efficient Max-log -MAP Decoder

TL;DR: A modified version of the ACS, known as Compare-Add-Select (CSA) has been used in this paper and it is asserted that for the proposed architecture, there is a 50% reduction in both area and power without compromising the performance when compared to the conventional architecture.