Showing papers by "Dominique Drouin published in 2022"

Exploiting Non-idealities of Resistive Switching Memories for Efficient Machine Learning

Abstract: Novel computing architectures based on resistive switching memories (also known as memristors or RRAMs) have been shown to be promising approaches for tackling the energy inefficiency of deep learning and spiking neural networks. However, resistive switch technology is immature and suffers from numerous imperfections, which are often considered limitations on implementations of artificial neural networks. Nevertheless, a reasonable amount of variability can be harnessed to implement efficient probabilistic or approximate computing. This approach turns out to improve robustness, decrease overfitting and reduce energy consumption for specific applications, such as Bayesian and spiking neural networks. Thus, certain non-idealities could become opportunities if we adapt machine learning methods to the intrinsic characteristics of resistive switching memories. In this short review, we introduce some key considerations for circuit design and the most common non-idealities. We illustrate the possible benefits of stochasticity and compression with examples of well-established software methods. We then present an overview of recent neural network implementations that exploit the imperfections of resistive switching memory, and discuss the potential and limitations of these approaches.

A Self-Aligned Structure based on V-groove for Accurate Silicon Bridge Placement

Abstract: As a lower cost alternative to silicon interposers with through silicon vias (TSVs), silicon bridges have been developed for high-performance computing (HPC) and/or heterogeneous integration. One of the most important steps of this advanced packaging technology is the accurate placement of the silicon bridge die with the organic substrate or with the dies requiring the high-density interconnections. In this paper, we demonstrated a novel mechanism for the straightforward and accurate insertion of silicon bridges into substrates. More specifically, mechanical fiducial in the form of V-groove were etch into the back side of functional bridges comprising Cu pillars, high-density Cu traces and insulating layers on their front side. Correspondingly, 4 SAC305 solder spheres were attached onto the substrate through thermal reflow to anchor the bridge. During the silicon bridge placing process, these 4 couples of concave and convex structures would pair and align each other automatically, determining the x, y and z final position of the silicon bridge. Experimental results showed that with such self-aligned structures, the placement drift of the silicon bridge could be confined to 2.5 μm.

Voltage-dependent synaptic plasticity: Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential

Abstract: This study proposes voltage-dependent-synaptic plasticity (VDSP), a novel brain-inspired unsupervised local learning rule for the online implementation of Hebb’s plasticity mechanism on neuromorphic hardware. The proposed VDSP learning rule updates the synaptic conductance on the spike of the postsynaptic neuron only, which reduces by a factor of two the number of updates with respect to standard spike timing dependent plasticity (STDP). This update is dependent on the membrane potential of the presynaptic neuron, which is readily available as part of neuron implementation and hence does not require additional memory for storage. Moreover, the update is also regularized on synaptic weight and prevents explosion or vanishing of weights on repeated stimulation. Rigorous mathematical analysis is performed to draw an equivalence between VDSP and STDP. To validate the system-level performance of VDSP, we train a single-layer spiking neural network (SNN) for the recognition of handwritten digits. We report 85.01 ± 0.76% (Mean ± SD) accuracy for a network of 100 output neurons on the MNIST dataset. The performance improves when scaling the network size (89.93 ± 0.41% for 400 output neurons, 90.56 ± 0.27 for 500 neurons), which validates the applicability of the proposed learning rule for spatial pattern recognition tasks. Future work will consider more complicated tasks. Interestingly, the learning rule better adapts than STDP to the frequency of input signal and does not require hand-tuning of hyperparameters.

Miniaturizing neural networks for charge state autotuning in quantum dots

Abstract: A key challenge in scaling quantum computers is the calibration and control of multiple qubits. In solid-state quantum dots, the gate voltages required to stabilize quantized charges are unique for each individual qubit, resulting in a high-dimensional control parameter space that must be tuned automatically. Machine learning techniques are capable of processing high-dimensional data - provided that an appropriate training set is available - and have been successfully used for autotuning in the past. In this paper, we develop extremely small feed-forward neural networks that can be used to detect charge-state transitions in quantum dot stability diagrams. We demonstrate that these neural networks can be trained on synthetic data produced by computer simulations, and robustly transferred to the task of tuning an experimental device into a desired charge state. The neural networks required for this task are sufficiently small as to enable an implementation in existing memristor crossbar arrays in the near future. This opens up the possibility of miniaturizing powerful control elements on low-power hardware, a significant step towards on-chip autotuning in future quantum dot computers.

Insertion of an Ultrathin Interfacial Aluminum Layer for the Realization of a Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction

Abstract: Herein, the effect of a 2 nm thin aluminum layer inserted between the ferroelectric layer and the top electrode in a TiN/ Hf0.5Zr0.5O2 /TiN stack deposited by reactive magnetron sputtering is investigated. The oxidation of the interfacial layer during annealing due to scavenging of the Hf0.5Zr0.5O2 impacts both the ferroelectric properties and the electrical conductivity of the junction. It is shown that the overall conductivity of the junction is boosted 20 folds while the resistance ratio between the positive and negative polarization states is increased from 1.3 up to 3.7. Through a systematic analysis of programming conditions, pulse duration, and height, we show that both the remanent polarization and On/Off current ratio can be enhanced at the expanse of the endurance leading to a trade‐off.

Multiple material stack grayscale patterning using electron-beam lithography and a single plasma etching step

Abstract: In this paper, we present a novel method to perform grayscale electron-beam lithography on multilayer stacks where the pattern transfer is done in a single plasma etching step. Due to the differences in material etch rates in the stack, the shape of the resist after development vs the shape of the multilayer stack after etching is significantly different. To be able to reach the desired shape in the multilayer stack, the final resist dose is defined by an etching calibration curve that describes the relationship between the electron-beam dose and the remaining materials thickness after plasma etching. With this method, a resistive memory crossbar array is fabricated with a height resolution of 10 nm and nanoscale dimension devices.

Moisture Diffusion Inside the BEOL of an FC-PBGA Package

Abstract: Moisture diffusion into the back-end-of-line (BEOL) can be critical for the reliability of electronic devices. With the objective of studying moisture diffusion into critical areas, such as the silicon–organic substrate interfaces of a flip chip plastic ball grid array (FC-PBGA), a multitude of impedance sensors sensitive to moisture are integrated inside the BEOL of a $17\times17$ mm silicon die. The sensors are read by a dedicated custom circuit that allows accurate characterization of the moisture with in situ spatial measurements. This article presents the results obtained by the experimental acquisition system on the FC-PBGA module under a high-relative humidity (RH) level of up to 75%. This study shows the moisture behavior of the multiwalled carbon nanotube (MWCNT) sensors inside the BEOL during absorption and desorption. The behavior initially follows Fick’s law, with a constant increase in the RH. For long-term tests of more than 400 h, an asymptotic behavior is observed; when the concentration of a sensor reaches a value close to saturation, a two-dimensional finite-difference method (2D FDM) is used to estimate the saturation value. Thanks to the large number of sensors distributed on the BEOL, we first detect, during an absorption test, an increase in the RH. This increase is due, first of all, to a lateral moisture front with a constant velocity of about $90 ~\mu \text{m}$ /h moving through the underfill. Then, after 30 h of storage, a more complex diffusion through the organic substrate occurs, affecting the BEOL.

Memristor-Based Cryogenic Programmable DC Sources for Scalable In Situ Quantum-Dot Control

Abstract: Current quantum systems based on spin qubits are controlled by classical electronics located outside the cryostat. This approach creates a major wiring bottleneck, which is one of the main roadblocks toward scalable quantum computers. Thus, we propose a scalable memristor-based programmable dc source that can perform biasing of quantum dots (QDs) inside the cryostat. This novel cryogenic approach would enable to control the applied voltage on the electrostatic gates by programming the resistance of the memristors, thus storing in the latter the appropriate conditions to form the QDs. In this study, we first demonstrate multilevel resistance programming of TiO2 memristors at 4.2 K, an essential feature to achieve voltage tunability of the memristor-based dc source. We then report hardware-based simulations of the electrical performance of the proposed dc source. A cryogenic TiO2 memristor model fit on our experimental data at 4.2 K was used to show a 1 V voltage range and 100 $\mu \text{V}$ resolution in situ memristor-based dc source. Finally, we simulate the biasing of double QDs (DQDs), enabling 120 s stability diagrams. This demonstration is a first step toward advanced cryogenic applications for resistive memories, such as cryogenic control electronics for quantum computers.

Hybrid cross correlation and line-scan alignment strategy for CMOS chips electron-beam lithography processing

Abstract: In this paper, we show an alignment strategy based on a hybrid strategy using cross correlation and line-scan alignment to address the challenge for CMOS integrated circuit postprocessing using electron-beam lithography. Due to design rules imposed by the foundries at the 130 nm node and below, classical line-scan alignment is not possible, and marker shapes are limited. The shape of the marker is essential for cross-correlation alignment. By measuring accurately the alignment offset between two lithography steps with different marker shapes compatible with the design rules, we tested the influence of the marker shape in the performance of the cross-correlation alignment. We present a method based on a white noise generated array to design high-performance markers for cross correlation, compatible with CMOS technology, by increasing the sharpness of their autocorrelation peak. We show that the alignment performances can even be improved using a hybrid strategy with cross-correlation and line-scan alignment and reaches a mean offset of 5.2 nm on a CMOS substrate.