Michael P. Belyansky

TL;DR: In this article, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow, which results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current improvement of 11%/20%.

TL;DR: In this paper, the authors propose to react the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi 2, NiSi, or PdSi) within a transistor gate.

TL;DR: In this paper, the authors present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay.

TL;DR: In this article, a high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels.

TL;DR: In this paper, a method of fabricating a semiconductor device structure, which includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small-grained semiconductor materials, within a recess, and then annealing the resultant structure.