Proceedings ArticleDOI
The MorphoSys dynamically reconfigurable system-on-chip
Guangming Lu,H. Singh,Ming-Hau Lee,Nader Bagherzadeh,Fadi J. Kurdahi,Eliseu M. Chaves Filho,V. Castro-Alves +6 more
- pp 152-160
TLDR
Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors.Abstract:
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors. Meanwhile, MorphoSys can provide the potential hardware platforn for the evolvable hardware (EH) simulation with the help of the software.read more
Citations
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Patent
Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
TL;DR: In this article, a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing is proposed, which includes a plurality of heterogeneous computational elements coupled to an interconnection network.
Patent
Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
TL;DR: In this article, the configuration of a new category of integrated circuitry for adaptive computing is discussed and various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information.
Patent
Task definition for specifying resource requirements
TL;DR: Task definitions are used by a task scheduler and prioritizer to allocate task operations to a plurality of processing units as mentioned in this paper, where the task definition is an electronic record that specifies resources needed by, and other characteristics of, a task to be executed.
Patent
Systems and methods for software extensible multi-processing
TL;DR: In this paper, a system for processing applications includes processor nodes and links interconnecting the processor nodes, each node includes a processing element, a software extensible device, and a communication interface.
Book ChapterDOI
Evolving hardware by dynamically reconfiguring xilinx FPGAs
Andres Upegui,Eduardo Sanchez +1 more
TL;DR: Three techniques for performing hardware evolution by exploiting the capacities of Virtex families are summarized, and a modular based evolution, with pre-placed and routed components, provides a coarse grain approach and two techniques for directly modifying LUT contents on hard macros provide a fine grained evolution.
References
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