Electronic Textiles (e-textiles) are fabrics that feature electronics and interconnections woven into them, presenting physical flexibility and typical size that cannot be achieved with other existing electronic manufacturing techniques. Components and interconnections are intrinsic to the fabric and thus are less visible and not susceptible of becoming tangled or snagged by surrounding objects. E-textiles can also more easily adapt to fast changes in the computational and sensing requirements of any specific application, this one representing a useful feature for power management and context awareness. The vision behind wearable computing foresees future electronic systems to be an integral part of our everyday outfits. Such electronic devices have to meet special requirements concerning wearability. Wearable systems will be characterized by their ability to automatically recognize the activity and the behavioral status of their own user as well as of the situation around her/him, and to use this information to adjust the systems' configuration and functionality. This review focuses on recent advances in the field of Smart Textiles and pays particular attention to the materials and their manufacturing process. Each technique shows advantages and disadvantages and our aim is to highlight a possible trade-off between flexibility, ergonomics, low power consumption, integration and eventually autonomy.

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Wearable Electronics and Smart Textiles: A Critical Review

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

In this paper, an overview of antenna design for passive radio frequency identification (RFID) tags is presented. We discuss various requirements of such designs, outline a generic design process including range measurement techniques and concentrate on one practical application: RFID tag for box tracking in warehouses. A loaded meander antenna design for this application is described and its various practical aspects such as sensitivity to fabrication process and box content are analyzed. Modeling and simulation results are also presented which are in good agreement with measurement data.

Antenna design for UHF RFID tags: a review and a practical application

The worldwide thirst for portable consumer electronics in the 1990s had an enormous impact on portable power. Lithium ion batteries, in which lithium ions shuttle between an insertion cathode (e.g., LiCoO2) and an insertion anode (e.g., carbon), emerged as the power source of choice for the highperformance rechargeable-battery market. The performance advantages were so significant that lithium ion batteries not only replaced Ni-Cd batteries but left the purported successor technology, nickel-metal hydride, in its wake.1 The thick metal plates of * To whom correspondence should be addressed. J.W.L: e-mail, jwlong@ccs.nrl.navy.mil; telephone, (+1)202-404-8697. B.D.: e-mail, bdunn@ucla.edu; telephone, (+1)310-825-1519. D.R.R.: e-mail, rolison@nrl.navy.mil; telephone, (+1)202-767-3617. H.S.W.: e-mail, white@chem.utah.edu; telephone, (+1)810-585-6256. † Naval Research Laboratory. ‡ UCLA. § University of Utah. 4463 Chem. Rev. 2004, 104, 4463−4492

Three-dimensional battery architectures.

This paper presents a thermal modeling analysis of the impact of the introduction of a backside power delivery network (BS-PDN) and assesses the trade-off between the beneficial and detrimental thermal consequences of this BS-PDN. In the BS-PDN concept, the power delivery network is moved to the backside of the chip, which enables enhanced system performance, increased chip-area utilization and reduced fine metal pitch BEOL complexity. The connectivity between the backside metals of the PDN and the transistors is provided by means of micro or nano through-Si vias, which requires an extreme thinning of the Si substrate. The potential self-heating issue due to this substrate thinning is the main thermal concern for the backside PDN concept. This paper focuses on the thermal modeling study for a TSV-last BS-PDN concept, for which the TSVs through the Si substrate are processed in the last step, after the processing of the front-end and power rails. A unit cell thermal finite element model of the via-last BS-PDN test case is used with size dependent thermal properties, derived from dedicated nanoscale Monte Carlo simulations. The simulation studies assess the thermal impact of the Si substrate thickness, the backside metals, and the density of the µTSVs.

Package level thermal analysis of backside power delivery network (BS-PDN) configurations

For various 3D integration schemes, such as Collective Die to wafer stacking (CoD2W) and Die to wafer (D2W) bonding, the thermal budget needs to be well below 250°C due to the presence of temporary bonding materials. In this paper we, present a new PECVD SiCN layer deposited at 175°C, optimized for hybrid bonding applications. The layer provides void-free wafer to wafer bonding interface demonstrated by high bond strength even at a post bond annealing (PBA) temperature of 200°C and devoid of any outgassing voids until 350°C. Additionally, it has been verified that the layer has excellent moisture and as electrical barrier properties.

Low temperature SiCN as dielectric for hybrid bonding

Schaltdiagramm für die orthogonale Anordnung von Mikrostrukturen

Multi-dies stack 3D-ICs are an extension of traditional 2-dies 3D-ICs to address the memory wall and footprint problems. This paper presents a complete Place-and-Route (PnR) flow to enable 3-dies stacked 3D-ICs from netlist partitioning to timing analysis, including original cross-dies co-optimization steps. The proposed flow is based on Integrity™ 3D-IC tool from Cadence. To demonstrate the flow, openPITON-T1 Tile design with IMEC N2 Process Design Kit (PDK) is used. The same design is implemented in normal 2D PnR flow and the proposed 3-dies stack flow. Our results show that a 3-dies stack design can achieve up to 11.4% increase in effective frequency and 50% less system footprint when compared with its 2D counterpart.

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs

The present invention is related to a chuck for the collective bonding of semiconductor dies to a target wafer. The chuck of the invention is a substrate comprising on one of its flat surfaces, a number of films of carbon nanotubes, said films being deposited on a number of die placement sites. The CNT films are obtainable by growing the nanotubes on the die placement sites, i.e. the CNTs are attached to the surface of the chuck at one end and the CNTs extend outward from said surface. Preferably the CNT films are deposited in a number of recesses etched in the surface of the chuck. The recesses may have different depths, in order to compensate height differences between a plurality of dies. The CNT films are resilient and thereby give a degree of compliance to the chuck. The films may also perform an adhesive force on the dies that is high in shear direction, which allows the placement accuracy of the dies to be well maintained during bonding. The adhesion force in the normal direction is lower but still sufficient to hold the dies firmly during pre-treatments such as wet cleaning and plasma treatment. Release of the chuck from the bonded dies is easy due to the low normal adhesive force. The CNT films may be pre-compressed so as to lend a higher stability to the films.

Eric Beyne

Papers

Package level thermal analysis of backside power delivery network (BS-PDN) configurations

Low temperature SiCN as dielectric for hybrid bonding

Schaltdiagramm für die orthogonale Anordnung von Mikrostrukturen

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs

Chuck for collective bonding of semiconductor dies