Electronic Textiles (e-textiles) are fabrics that feature electronics and interconnections woven into them, presenting physical flexibility and typical size that cannot be achieved with other existing electronic manufacturing techniques. Components and interconnections are intrinsic to the fabric and thus are less visible and not susceptible of becoming tangled or snagged by surrounding objects. E-textiles can also more easily adapt to fast changes in the computational and sensing requirements of any specific application, this one representing a useful feature for power management and context awareness. The vision behind wearable computing foresees future electronic systems to be an integral part of our everyday outfits. Such electronic devices have to meet special requirements concerning wearability. Wearable systems will be characterized by their ability to automatically recognize the activity and the behavioral status of their own user as well as of the situation around her/him, and to use this information to adjust the systems' configuration and functionality. This review focuses on recent advances in the field of Smart Textiles and pays particular attention to the materials and their manufacturing process. Each technique shows advantages and disadvantages and our aim is to highlight a possible trade-off between flexibility, ergonomics, low power consumption, integration and eventually autonomy.

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Wearable Electronics and Smart Textiles: A Critical Review

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

In this paper, an overview of antenna design for passive radio frequency identification (RFID) tags is presented. We discuss various requirements of such designs, outline a generic design process including range measurement techniques and concentrate on one practical application: RFID tag for box tracking in warehouses. A loaded meander antenna design for this application is described and its various practical aspects such as sensitivity to fabrication process and box content are analyzed. Modeling and simulation results are also presented which are in good agreement with measurement data.

Antenna design for UHF RFID tags: a review and a practical application

The worldwide thirst for portable consumer electronics in the 1990s had an enormous impact on portable power. Lithium ion batteries, in which lithium ions shuttle between an insertion cathode (e.g., LiCoO2) and an insertion anode (e.g., carbon), emerged as the power source of choice for the highperformance rechargeable-battery market. The performance advantages were so significant that lithium ion batteries not only replaced Ni-Cd batteries but left the purported successor technology, nickel-metal hydride, in its wake.1 The thick metal plates of * To whom correspondence should be addressed. J.W.L: e-mail, jwlong@ccs.nrl.navy.mil; telephone, (+1)202-404-8697. B.D.: e-mail, bdunn@ucla.edu; telephone, (+1)310-825-1519. D.R.R.: e-mail, rolison@nrl.navy.mil; telephone, (+1)202-767-3617. H.S.W.: e-mail, white@chem.utah.edu; telephone, (+1)810-585-6256. † Naval Research Laboratory. ‡ UCLA. § University of Utah. 4463 Chem. Rev. 2004, 104, 4463−4492

Three-dimensional battery architectures.

During the manufacturing of 3D stacked-die packaging structures, different operations such as micro bumps formation, underfilling, flip chip and overmold curing will introduce residual stresses, which will interact with subsequent service loads applied to the package and may also influence the growth of cracks in critical locations. In this work, the packaging of a 3D-RAM mounted on a logic die is simulated taking the thermal history into account by simulating the main process steps and by adapting the mechanical stiffness of the materials. The resulting stress/strain tensors are taken as initial condition of the following step and the mechanical properties of the new materials added to the process are adapted. The resulting stresses and strains at every step are extracted from the model to identify the most critical processing steps. A die to wafer approach is used for the stacking process as it allows the integration of heterogeneous and different die size. In this work we show the simulation results after each processing step for two die stacking approaches: (a) mold wafer reconstruction, (b) window wafer reconstruction. In the first case, high warpage is observed. In the second case, warpage is reduced but high stress concentration is observed in the logic die.

https://ieeexplore.ieee.org/iel7/6573226/6575533/06575543.pdf

Thermo mechanical challenges for processing and packaging stacked ultrathin wafers

Copper plasticity effects in TSV middle and backside TSV last integration flows are analyzed using an advanced 3D TCAD simulator with model parameters calibrated to match experimental data. In this work, a low thermal budget TSV last integration flow is considered. In contrast to the TSV middle flow, the TSV last flow studied here exhibits insignificant TSV pumping, M1 metal thinning or M1 metal resistance increase. The difference in residual stress profiles in BEOL structure for TSV middle and TSV last processes indicates that the process sequence must be optimized in order to minimize the reliability risks. The mobility change in active silicon for the TSV last process is lower as compared to that for the TSV middle process at room temperature due to the lower temperature excursions during the TSV last integration. This study demonstrates that the TSV integration flow must be designed and selected carefully to meet specific performance and reliability requirements.

Analysis of copper plasticity impact in TSV-middle and backside TSV-last fabrication processes

In this paper we report on the first theoretical analysis of feeding planar antennas with the slotline mode of the CPW. The analysis is carried out using a mixed potential integral equation formulation, MPIE, solved with the method of moments, MoM. The analysis is applied on a CPW-fed cusp antnna The theoretical results include the return loss and the radiation patterns associated with both the coplanar and the slotline modes. Experiments are also performed and their results for the coplanar mode are presented. The agreement between theory and experiments for the coplanar mode validates the theory and the presented results for the slotline mode.

Coplanar Versus Slotline Mode in Exciting CPW-FED Planar Antennas

The electronic subsystem of wearable and implantable devices is constructed using board-level and package-level integration technology and this limits the achievable miniaturization. We will show that this limitation can be overcome by emerging wafer-level integration methods such as chip-in-wire technology. These technologies can even achieve mechanically bendable and stretchable subsystems.

Design and Integration Technology for Miniature Medical Microsystems

The invention relates to a connection-substrate for at least one electronic component. Said substrate comprises a flat substrate body in whose flat surface internal contact projections (3) are recessed by partial removal or deformation (2, 8), for the flip-chip contacting rod of a component or, optionally, external contact projections (9) for connection to a printed circuit board. The production of said contact-projections in a hot stamping method or by means of laser removal enables very small projections to be produced in a narrower grid than current chip-connections.

Eric Beyne

Papers

Thermo mechanical challenges for processing and packaging stacked ultrathin wafers

Analysis of copper plasticity impact in TSV-middle and backside TSV-last fabrication processes

Coplanar Versus Slotline Mode in Exciting CPW-FED Planar Antennas

Design and Integration Technology for Miniature Medical Microsystems

Electronic component module and method for the production thereof