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Eric Beyne
Researcher at Katholieke Universiteit Leuven
Publications - 664
Citations - 10608
Eric Beyne is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Wafer & Die (integrated circuit). The author has an hindex of 44, co-authored 626 publications receiving 9619 citations. Previous affiliations of Eric Beyne include IMEC & Siemens.
Papers
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Proceedings ArticleDOI
Constant impedance scaling paradigm for interconnect synthesis
J. Balachandran,Steven Brebels,Geert Carchon,Maarten Kuijk,W. De Raedt,Bart Nauwelaers,Eric Beyne +6 more
TL;DR: A constant impedance scaling paradigm is proposed for systematic synthesis of complete interconnects physical parameters from system level performance metrics such as delay, power and wiring density.
Journal ArticleDOI
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects
Luka Kljucar,Mario Gonzalez,Kristof Croes,Ingrid De Wolf,Joke De Messemaeker,Gayle Murdoch,P. Nolmans,Joeri De Vos,Jürgen Bömmels,Eric Beyne,Zsolt Tőkei +10 more
TL;DR: The data show a correlation between via density and reliability for both passivation modules, where a higher via density reduces the number of failures.
Patent
Method of fabricating a laminated printed circuit board
Eric Beyne,Francois Lechleiter +1 more
TL;DR: In this paper, a method and apparatus of fabricating a core laminate Printed Circuit Board structure with highly planar external surfaces is provided, where a pre-formed flat material including a first resinous sub-material and a second carrier sub-surface is used to planarize external surfaces.
Proceedings ArticleDOI
3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers
T. Buisson,I. De Preter,Samuel Suhard,Kevin Vandersmissen,Patrick Jaenen,Thomas Witters,G. Jamieson,Anne Jourdain,S. Van Huylenbroeck,A. La Manna,Gerald Beyer,Eric Beyne +11 more
TL;DR: In this paper, the fabrication of small pitch micro-bumps on thinned wafers after through silicon vias (TSV) reveal and back side passivation is reported, where the micro-bump scaling involves a reduction of the overall solder volume.
Journal ArticleDOI
Convolution-Based Fast Thermal Model for 3-D-ICs: Transient Experimental Validation
Federica Lidia Teresa Maggioni,Vladimir Cherman,Herman Oprins,Eric Beyne,Ingrid De Wolf,Martine Baelmans +5 more
TL;DR: In this paper, the transient experimental validation of the convolution-based fast thermal model (FTM) for 3-D integrated circuits is presented, and the model has been validated with respect to case studies concerning duty cycles of different durations.