Eric Beyne

TL;DR: This paper focusses on an experimental inductive link study based on S-parameter measurements up to 67 GHz for 3D stacked chip to chip communication, complemented by a calibrated HFSS model for coupling between two chips that is then extended to stacks with up to eight chips.

TL;DR: Multilayer thin film technology is proposed as a bridge- technology between the very high density IC technology and the coarse standard PCB technology, and is also a key enabling technology for the realization of true SiP solutions, combining multiple SoC IC's with other components and also integrating passive compon- ents in its layers.

TL;DR: In this paper, the authors describe ultra-fine pitch 3D integration development using wafer level Cu/insulator hybrid bonding approach on 300mm substrate, and demonstrate and characterize vertical interconnects formed via face-to-face waferto-wafer (W2W) bonding.

TL;DR: In this article, a test structure for in-situ monitoring of electromigration in a flip chip connection is proposed, where small resistance changes at the cathodic and anodic sides can be mounted separately.

TL;DR: In this paper, defects in the overall thinning process flow will become a major element of focus in the future and fundamental understanding of the potential defects and their impact on devices is therefore needed to minimize their recurrence.