Eric Beyne

TL;DR: In this paper, a laser-based fault isolation methodologies for the localization of open and short failures in $1 \times 5 \,\,\mu \text{m}$ via-last through-silicon via (TSV) structures for 3-D system-on-chip (SoC) integration is presented.

TL;DR: The contribution of the package substrate and die attach process to the redistribution of mechanical stress inside the 3D stacked IC is more significant than the one of the EMC and that the influence of packaging on the shape and amplitude of local stress around the inter-die interconnects (micro-bumps) is not significant as mentioned in this paper.

TL;DR: In this paper, the authors compared the performance of standard NiAu/SAC (SnAgCu) solder bumps and Cu pillar bumps in terms of their electromigration behavior, and found that the pillar bumps outperformed the standard solder flip chip bumps due to the fast formation of an intermetallic phase which covers the full solder stand-off height.

TL;DR: In this article, a method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed, in which the wafer is bonded by a direct bonding technique to form a wafer assembly, and multiple IC devices are provided with metal contact structures.

TL;DR: A transient fast thermal model methodology for packaged 3D stacked ICs is presented, whose core is constituted by a highly resolved, convolution-based algorithm, which allows to compute the temperature increase due to a generic, time varying, power map in a stack configuration.