Electronic Textiles (e-textiles) are fabrics that feature electronics and interconnections woven into them, presenting physical flexibility and typical size that cannot be achieved with other existing electronic manufacturing techniques. Components and interconnections are intrinsic to the fabric and thus are less visible and not susceptible of becoming tangled or snagged by surrounding objects. E-textiles can also more easily adapt to fast changes in the computational and sensing requirements of any specific application, this one representing a useful feature for power management and context awareness. The vision behind wearable computing foresees future electronic systems to be an integral part of our everyday outfits. Such electronic devices have to meet special requirements concerning wearability. Wearable systems will be characterized by their ability to automatically recognize the activity and the behavioral status of their own user as well as of the situation around her/him, and to use this information to adjust the systems' configuration and functionality. This review focuses on recent advances in the field of Smart Textiles and pays particular attention to the materials and their manufacturing process. Each technique shows advantages and disadvantages and our aim is to highlight a possible trade-off between flexibility, ergonomics, low power consumption, integration and eventually autonomy.

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Wearable Electronics and Smart Textiles: A Critical Review

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

In this paper, an overview of antenna design for passive radio frequency identification (RFID) tags is presented. We discuss various requirements of such designs, outline a generic design process including range measurement techniques and concentrate on one practical application: RFID tag for box tracking in warehouses. A loaded meander antenna design for this application is described and its various practical aspects such as sensitivity to fabrication process and box content are analyzed. Modeling and simulation results are also presented which are in good agreement with measurement data.

Antenna design for UHF RFID tags: a review and a practical application

The worldwide thirst for portable consumer electronics in the 1990s had an enormous impact on portable power. Lithium ion batteries, in which lithium ions shuttle between an insertion cathode (e.g., LiCoO2) and an insertion anode (e.g., carbon), emerged as the power source of choice for the highperformance rechargeable-battery market. The performance advantages were so significant that lithium ion batteries not only replaced Ni-Cd batteries but left the purported successor technology, nickel-metal hydride, in its wake.1 The thick metal plates of * To whom correspondence should be addressed. J.W.L: e-mail, jwlong@ccs.nrl.navy.mil; telephone, (+1)202-404-8697. B.D.: e-mail, bdunn@ucla.edu; telephone, (+1)310-825-1519. D.R.R.: e-mail, rolison@nrl.navy.mil; telephone, (+1)202-767-3617. H.S.W.: e-mail, white@chem.utah.edu; telephone, (+1)810-585-6256. † Naval Research Laboratory. ‡ UCLA. § University of Utah. 4463 Chem. Rev. 2004, 104, 4463−4492

Three-dimensional battery architectures.

This paper presents a new approach to designing robust circuits implementing integrated passive devices (IPD) for radio frequency applications fabricated with thin film technology. IMEC's thin film rf-IPD technology allows defining high-accuracy and high-Q passive components, e.g. transmission lines, inductors, resistors and various types of capacitors, in a cost-effective process. This paper uses a case study based on electrical characterization data for a LC tank based filter using Ta2O5 and BCB dielectrics. The effect of the variations in the fabrication process on the performance of the filter and the resulting feedback to the manufacturing of the RF - IPDs is studied. Deterministic approaches are unable to take into account actual variability in design and manufacturing without over-dimensioning the design or assuming a too pessimistic view on the actual characteristics. The probabilistic design approach can be used to align the design with the realistic manufacturing tolerances so that the final design will be always reliable for the given processing variations.

Probabilistic design approach for integrated passive devices in RF applications

Imec is developing two TSV flavors for Si thicknesses of 50 and 100 μm for various wafer level packaging (WLP) applications where thin dice are stacked and electrically connected to each other through post CMOS processed TSVs and microbumps. As a differentiator, these TSV technologies use spin-on dielectric polymers as the insulating liner. A three-mask process sequence is implemented for fabrication of both TSV types; however, the TSV shape, the process flow, and the Si thickness are different for each one of them. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for post CMOS compatibility. For both TSV types, electrically yielding TSV connected daisy chains are measured on the fabricated wafers and the reliability of the TSVs while undergoing thermal cycle tests is analyzed.

Fabrication and Electrical Evaluation of Via Last Polymer Liner TSVs

In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1-<inline-formula> <tex-math notation="LaTeX">$\mathrm {W}/{\mathrm {mm}}^{2}$ </tex-math></inline-formula> power-density target for high-performance computing (HPC) systems, a 25-high-<inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula>-factor (300 MHz), 150-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>-thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m} V_{\mathrm {DD}}$ </tex-math></inline-formula>-bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>-horizontal-pitch nano- through-silicon via (<inline-formula> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula>TSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency <inline-formula> <tex-math notation="LaTeX">$\eta \,\,=83$ </tex-math></inline-formula>% can be obtained for 1-<inline-formula> <tex-math notation="LaTeX">$\mathrm {W}/{\mathrm {mm}}^{2}$ </tex-math></inline-formula> power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively.

Efficient Backside Power Delivery for High-Performance Computing Systems

This IP session will consist of three presentations. A summary of each presentation is given below.

Eric Beyne

Papers

Probabilistic design approach for integrated passive devices in RF applications

Fabrication and Electrical Evaluation of Via Last Polymer Liner TSVs

Efficient Backside Power Delivery for High-Performance Computing Systems

IP Session on Chiplet: Design, Assembly, and Test