Showing papers by "Errol Antonio C. Sanchez published in 2013"

Method of depositing a silicon germanium tin layer on a substrate

Abstract: Methods of depositing silicon germanium tin (SiGeSn) layer on a substrate are disclosed herein. In some embodiments, a method may include co-flowing a silicon source, a germanium source, and a tin source comprising a tin halide to a process chamber at a temperature of about 450 degrees Celsius or below and a pressure of about 100 Torr or below to deposit the SiGeSn layer on a first surface of the substrate. In some embodiments, the tin halide comprises tin tetrachloride (SnCl4).

Method of epitaxial doped germanium tin alloy formation

Abstract: A method for forming germanium tin layers and the resulting embodiments are described. A germanium precursor and a tin precursor are provided to a chamber, and an epitaxial layer of germanium tin is formed on the substrate. The germanium tin layer is selectively deposited on the semiconductor regions of the substrate and can include thickness regions of varying tin and dopant concentrations. The germanium tin layer can be selectively deposited by either alternating or concurrent flow of a halide gas to etch the surface of the substrate.

Highly Selective Dry Etching of Germanium over Germanium–Tin (Ge1–xSnx): A Novel Route for Ge1–xSnx Nanostructure Fabrication

Abstract: We present a new etch chemistry that enables highly selective dry etching of germanium over its alloy with tin (Ge1–xSnx). We address the challenges in synthesis of high-quality, defect-free Ge1–xSnx thin films by using Ge virtual substrates as a template for Ge1–xSnx epitaxy. The etch process is applied to selectively remove the stress-inducing Ge virtual substrate and achieve strain-free, direct band gap Ge0.92Sn0.08. The semiconductor processing technology presented in this work provides a robust method for fabrication of innovative Ge1–xSnx nanostructures whose realization can prove to be challenging, if not impossible, otherwise.

Epitaxial chamber with customizable flow injection

Abstract: Apparatus for processing a substrate in a process chamber are provided here. In some embodiments, a gas injector for use in a process chamber includes a first set of outlet ports that provide an angled injection of a first process gas at an angle to a planar surface, and a second set of outlet ports proximate the first set of outlet ports that provide a pressurized laminar flow of a second process gas substantially along the planar surface, the planar surface extending normal to the second set of outlet ports.

Methods and apparatus for generating and delivering a process gas for processing a substrate

Abstract: Methods and apparatus for generating and delivering process gases for processing substrates are provided herein. In some embodiments, an apparatus for processing a substrate may include a container comprising a lid, a bottom, and a sidewall, wherein the lid, the bottom, and the sidewall define an open area; a solid precursor collection tray disposed within the open area; a gas delivery tube disposed within the open area and extending toward the solid precursor collection tray to provide a gas proximate the solid precursor collection tray; and a purge flow conduit coupled to the open area.

Electrical Characterization of GaP-Silicon Interface for Memory and Transistor Applications

Abstract: Process conditions of gallium phosphide (GaP) metal-organic chemical vapor deposition growth on silicon (Si) are optimized by material characterization. Thorough investigation of GaP-Si interface at this optimized growth condition is carried out by electrical characterization with the perspective of applying this heterostructure system for improving the performance of logic transistors and retention time of capacitorless single-transistor dynamic RAM (1T-DRAM). Fabricated GaP-Si heterojunction diodes exhibit an ON-OFF ratio of 108 with similar reverse current as the ideal device simulation results signify immunity to the existing antiphase domains. Finally, MOSFET devices with GaP source-drain having subthreshold swing of 70 mV/dec and an ON-OFF ratio of 105 are demonstrated.

Fabrication of GeSn-On-Insulator (GSOI) to enable monolithic 3D co-integration of logic and photonics

Abstract: In this work, we demonstrate the low temperature fabrication of high quality GeSn-On-Insulator (GSOI) which forms the crucial module for monolithic 3DIC. The use of GeSn and Ge overcomes many challenges of monolithic 3D integration, including the need for Si-compatible high-mobility and direct gap materials. Furthermore, we introduce excellent passivation of the semiconductor/buried oxide (BOX) interface which is crucial to the high performance of devices on the stacked layers.

Methods for chemical mechanical planarization of patterned wafers

Abstract: Methods for chemical mechanical planarization of patterned wafers are provided herein. In some embodiments, methods of processing a substrate having a first surface and a plurality of recesses disposed within the first surface may include: depositing a first material into the plurality of recesses to predominantly fill the plurality of recesses with the first material; depositing a second material different from the first material into the plurality of recesses and atop the substrate to fill the plurality of recesses and to form a layer atop the first surface; and planarizing the second material using a first slurry in a chemical mechanical polishing tool until the first surface is reached. In some embodiments, a second slurry, different than the first slurry, is used to planarize the substrate to a first level.

Method and apparatus for precursor delivery

Abstract: Methods and apparatus for delivering a gas mixture to a process chamber are provided herein. In some embodiments, a precursor delivery apparatus may include an ampoule having a body with a first volume to hold a liquid precursor, an inlet to receive the liquid precursor and a carrier gas, and an outlet to flow a gas mixture of the liquid precursor and the carrier gas from the ampoule; a first heater disposed proximate to or in the first volume to heat the liquid precursor disposed in the first volume proximate to or at a first location within the first volume where the liquid precursor contacts the carrier gas; and a heat transfer apparatus disposed about the body to at least one of provide heat to or remove heat from the ampoule.

Compact ampoule thermal management system

Abstract: Apparatus for thermal management of a precursor for use in substrate processing are provided herein. In some embodiments, an apparatus for thermal management of a precursor for use in substrate processing may include a body having an opening sized to receive a storage container having a liquid or solid precursor disposed therein, the body fabricated from thermally conductive material; one or more thermoelectric devices coupled to the body proximate the opening; and a heat sink coupled to the one or more thermoelectric devices.

Methods for depositing group III-V layers on substrates

Abstract: Methods for depositing a group III-V layer on a substrate are disclosed herein. In some embodiments a method includes depositing a first layer comprising at least one of a first Group III element or a first Group V element on a silicon-containing surface oriented in a direction at a first temperature ranging from about 300 to about 400 degrees Celsius; and depositing a second layer comprising second Group III element and a second Group V element atop the first layer at a second temperature ranging from about 300 to about 600 degrees Celsius.

GaP source-drain vertical transistor on bulk silicon for 1-transistor DRAM application

Abstract: GaP is proposed as source and drain material for 1-transistor DRAM application as it is nearly lattice matched to silicon and provides a valence band offset of ~ 1 eV Simulations of retention time for the proposed vertical structure indicate: large improvement over similar bulk silicon devices, ability to meet ITRS requirement and good scalability An MOCVD recipe is optimized for GaP growth on silicon and further characterized by fabricating electrical devices such as diodes and transistors indicating feasibility for usage in 1T-DRAM technology

Methods for depositing a tin-containing layer on a substrate

Abstract: Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides.

GaP source-drain SOI 1T-DRAM: Solving the key technological challenges

Abstract: SOI based GaP source drain 1T DRAM with silicon channel is proposed. Using BJT-latch based programing, it is shown that the scalability of GaP-SD 1T-DRAM can be extended up to 20nm. Nickel alloying of GaP is proposed as a method to reduce the sheet and contact resistance of GaP source and drain. Using nickel alloying, the ON-current of the GaP-SD transistor is improved by an order and the proper scalability behavior is established.