A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

/pdf/a-45nm-logic-technology-with-high-k-metal-gate-transistors-1fgej5i9ew.pdf

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

/pdf/review-semiconductor-piezoresistance-for-microsystems-2i2jehwa4g.pdf

Review: Semiconductor Piezoresistance for Microsystems

nextnano is a semiconductor nanodevice simulation tool that has been developed for predicting and understanding a wide range of electronic and optical properties of semiconductor nanostructures. The underlying idea is to provide a robust and generic framework for modeling device applications in the field of nanosized semiconductor heterostructures. The simulator deals with realistic geometries and almost any relevant combination of materials in one, two, and three spatial dimensions. It focuses on an accurate and reliable treatment of quantum mechanical effects and provides a self-consistent solution of the Schrodinger, Poisson, and current equations. Exchange-correlation effects are taken into account in terms of the local density scheme. The electronic structure is represented within the single-band or multiband kldrp envelope function approximation, including strain. The code is not intended to be a ldquoblack boxrdquo tool. It requires a good understanding of quantum mechanics. The input language provides a number of tools that simplify setting up device geometry or running repetitive tasks. In this paper, we present a brief overview of nextnano and present four examples that demonstrate the wide range of possible applications for this software in the fields of solid-state quantum computation, nanoelectronics, and optoelectronics, namely, 1) a realization of a qubit based on coupled quantum wires in a magnetic field, 2) and 3) carrier transport in two different nano-MOSFET devices, and 4) a quantum cascade laser.

nextnano: General Purpose 3-D Simulations

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

A detailed theoretical picture is given for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III–V channel metal-oxide-semiconductor field-effect transistors. For the technologically important in-plane biaxial and longitudinal uniaxial stress, changes in energy band splitting and warping, effective mass, and scattering are investigated by symmetry, tight-binding, and k⋅p methods. The results show both types of stress split the Si conduction band while only longitudinal uniaxial stress along ⟨110⟩ splits the Ge conduction band. The longitudinal uniaxial stress warps the conduction band in all semiconductors. The physics of the strain altered valence bands for Si, Ge, and III–V semiconductors are shown to be similar although the strain enhancement of hole mobility is largest for longitudinal uniaxial compression in ⟨110⟩ channel devices and channel materials with substantial differences between heavy and light hole masses such as Ge and GaAs. Furthermore, for all these materials,...

Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors

A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a twodimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo-Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 "wings," where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility

Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers

For the first time, the tunneling current in silicon nMOS structures with ultra-thin gate oxides has been studied both by numerically solving Schrodinger's equation and by using the WKB approximation, which explicitly includes the size quantization effects in the inversion layers. The numerical solution employs first-order perturbation within the one-band effective-mass approximation to calculate the lifetime of an inversion-layer quasi-bound state. The good agreement in the tunneling currents estimated with these two methods justifies the use of the WKB approximation in the direct tunneling regime. The range of validity of the WKB approximation is also discussed.

Modeling gate leakage current in nMOS structures due to tunneling through an ultra-thin oxide

For the first time, we show with simulation that the use of a metal gate/high-k stack offers improved mobility over polysilicon/high-k gates stacks while maintaining decreased gate leakage compared to conventional SiO/sub 2/ stacks, thus allowing high-performance transistor scaling to continue.

Inversion mobility and gate leakage in high-k/metal gate MOSFETs

We have developed a quantum anisotropic transport model for holes which, for the first time, allows mobility to be studied under both uniaxial and arbitrary stress in PMOS inversion layers. The anisotropic bandstructure of a 2D quantum gas is computed from a 6-band stress dependent k.p Hamiltonian. Our unique momentum-dependent scattering model also captures the anisotropy of scattering. A comprehensive study has been performed for uniaxial stress, biaxial stress, and their nonlinear interactions. The results are compared with device bending data and piezoresistance data, showing very good agreement.

Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Everett X. Wang

Papers

Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers

Modeling gate leakage current in nMOS structures due to tunneling through an ultra-thin oxide

Inversion mobility and gate leakage in high-k/metal gate MOSFETs

Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress