Fernando Medeiro

TL;DR: This paper describes the design and modeling of error Mechanisms in Sigma-Delta Modulators, and some of the techniques used in the design of SDOPT+FRIDGE, a set of tools for the Automatic Design of Sigma- Delta Modulators.

TL;DR: In this paper, a nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise, which is fabricated in a double-metal, single-poly 1.6μm CMOS technology and uses a novel, highly accurate CMOS circuit strategy to realize piecewise linear characteristics in the current-mode domain.

TL;DR: This paper presents a high-level synthesis tool that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core and is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.

TL;DR: A nonlinear penalty-like approach is proposed to define a cost function from the performance specifications and a group of heuristics are proposed to increase the probability of reaching the global minimum as well as to reduce CPU time during the optimization process.

TL;DR: In this article, the authors present a tool that starting from high-level specifications of switched-capacitor (SC) /spl Sigma//spl Delta/ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics.