다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

von Neumann architecture based computers isolate computation and storage (i.e. data is shuttled between computation blocks (processor) and memory blocks). The to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the Memory wall. Logic in-Memory (LIM)/In-Memory Computing (IMC) approaches aim to address this bottleneck by directly computing inside memory units thereby eliminating energy-intensive and time-consuming data movement. Several recent works in literature, propose realization of logic function(s) directly using arrays of emerging resistive memory devices (example- memristors, RRAM/ReRAM, PCM, CBRAM, OxRAM, STT-MRAM etc.), rather than using conventional transistors for computing. The logic/embedded-side of digital systems (like processors, micro-controllers) can greatly benefit from such LIM realizations. However, the pure storage-side of digital systems (example SSDs, enterprise storage etc.) will not benefit much from such LIM approaches as when memory arrays are used for logic they lose their core functionality of storage. Thus, there is the need for an approach complementary to existing LIM techniques, that's more beneficial for the storage-side of digital systems; one that gives compute capability to memory arrays not at the cost of their existing stored states. Fundamentally, this would require memory nanodevice arrays that are capable of storing and computing simultaneously. In this paper, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology which is complementary to existing LIM approaches in literature. Through extensive experiments we demonstrate novel SLIM bitcells (1T-1R/2T-1R) comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors. Proposed bitcells are capable of implementing both Memory and Logic operations simultaneously. Detailed programming scheme, array level implementation, and controller architecture are also proposed. Furthermore, to study the impact of proposed SLIM approach for real-world implementations, we performed analysis for two applications: (i) Sobel Edge Detection, and (ii) Binary Neural Network- Multi layer Perceptron (BNN-MLP). By performing all computations in SLIM bitcell array, huge Energy Delay Product (EDP) savings of ≈75× for 1T-1R (≈40× for 2T-1R) SLIM bitcell were observed for edge-detection application while EDP savings of ≈3.5× for 1T-1R (≈1.6× for 2T-1R) SLIM bitcell were observed for BNN-MLP application respectively, in comparison to conventional computing. EDP savings owing to reduction in data transfer between CPU ↔ memory is observed to be ≈780× (for both SLIM bitcells).

/pdf/slim-simultaneous-logic-in-memory-computing-exploiting-48akr75xhf.pdf

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.

Current-induced effective magnetic fields can provide efficient ways of electrically manipulating the magnetization of ultrathin magnetic heterostructures. Two effects, known as the Rashba spin orbit field and the spin Hall spin torque, have been reported to be responsible for the generation of the effective field. However, a quantitative understanding of the effective field, including its direction with respect to the current flow, is lacking. Here we describe vector measurements of the current-induced effective field in Ta|CoFeB|MgO heterostructrures. The effective field exhibits a significant dependence on the Ta and CoFeB layer thicknesses. In particular, a 1 nm thickness variation of the Ta layer can change the magnitude of the effective field by nearly two orders of magnitude. Moreover, its sign changes when the Ta layer thickness is reduced, indicating that there are two competing effects contributing to it. Our results illustrate that the presence of atomically thin metals can profoundly change the landscape for controlling magnetic moments in magnetic heterostructures electrically.

▲Current-induced effective field vector in Ta│CoFeB│MgO

Von Neumann architecture based computers isolate/physically separate computation and storage units i.e. data is shuttled between computation unit (processor) and memory unit to realize logic/ arithmetic and storage functions. This to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the memory wall. Logic in-Memory (LIM) approaches aim to address this bottleneck by computing inside the memory units and thereby eliminating the energy-intensive and time-consuming data movement. However, most LIM approaches reported in literature are not truly "simultaneous" as during LIM operation the bitcell can be used only as a Memory cell or only as a Logic cell. The bitcell is not capable of storing both the Memory/Logic outputs simultaneously. Here, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology that allows to implement both Memory and Logic operations simultaneously on the same bitcell in a non-destructive manner without losing the previously stored Memory state. Through extensive experiments we demonstrate the SLIM methodology using non-filamentary bilayer analog OxRAM devices with NMOS transistors (2T-1R bitcell). Detailed programming scheme, array level implementation and controller architecture are also proposed. Furthermore, to study the impact of introducing SLIM array in the memory hierarchy, a simple image processing application (edge detection) is also investigated. It has been estimated that by performing all computations inside the SLIM array, the total Energy Delay Product (EDP) reduces by ~ 40x in comparison to a modern-day computer. EDP saving owing to reduction in data transfer between CPU Memory is observed to be ~ 780x.

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices

In this manuscript, recent progress in the area of resistive random access memory (RRAM) technology which is considered one of the most standout emerging memory technologies owing to its high speed, low cost, enhanced storage density, potential applications in various fields, and excellent scalability is comprehensively reviewed. First, a brief overview of the field of emerging memory technologies is provided. The material properties, resistance switching mechanism, and electrical characteristics of RRAM are discussed. Also, various issues such as endurance, retention, uniformity, and the effect of operating temperature and random telegraph noise (RTN) are elaborated. A discussion on multilevel cell (MLC) storage capability of RRAM, which is attractive for achieving increased storage density and low cost is presented. Different operation schemes to achieve reliable MLC operation along with their physical mechanisms have been provided. In addition, an elaborate description of switching methodologies and current voltage relationships for various popular RRAM models is covered in this work. The prospective applications of RRAM to various fields such as security, neuromorphic computing, and non-volatile logic systems are addressed briefly. The present review article concludes with the discussion on the challenges and future prospects of the RRAM.

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Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications

In this review, a comprehensive survey of different oxide-based resistive random-access memories (RRAMs) for neuromorphic computing is provided. We begin with the history of RRAM development, physical mechanism of conduction, fundamental of neuromorphic computing, followed by a review of a variety of RRAM oxide materials (PCMO, HfOx, TaOx, TiOx, NiOx, etc.) with a focus on their application for neuromorphic computing. Our goal is to give a broad review of oxide-based RRAM materials that can be adapted to neuromorphic computing and to help further ongoing research in the field.

Oxide-based RRAM materials for neuromorphic computing

We report bi-directional domain wall (DW) motion along and against current flow direction in Co/Pt double stack wires with Ta capping. The bi-directionality is achieved by application of hard-axis magnetic field favoring and opposing the Dzyloshinskii-Moriya interaction (DMI), respectively. The speed obtained is enhanced when the hard-axis field favors the DMI and is along the current flow direction. Co/Pt double stack is a modification proposed for the high spin-orbit torque strength Pt/Co/Ta stack, to improve its thermal stability and perpendicular magnetic anisotropy (PMA). The velocity obtained reduces with increase in Pt spacer thickness due to reduction in DMI and enhances on increasing the Ta capping thickness due to higher SOT strength. The velocity obtained is as high as 530 m/s at a reasonable current density of 1 × 1012 A/m2 for device applications. The low anisotropy of the device coupled with the application of hard-axis field aids the velocity enhancement by preventing Walker breakdown.

/pdf/bi-directional-high-speed-domain-wall-motion-in-3icumi2fn6.pdf

Bi-directional high speed domain wall motion in perpendicular magnetic anisotropy Co/Pt double stack structures

The strength of spin-orbit torque in ferromagnetic structures is characterized by fieldlike and dampinglike effective fields. Conventionally, two distinct measurement approaches are employed to quantify the magnitude of the respective effective fields in structures with in-plane magnetic anisotropy. Here, we propose and demonstrate a self-validating method, which enables simultaneous quantification of both the fieldlike and dampinglike terms in structures with in-plane magnetic anisotropy. An analytical expression is derived and validated by harmonic Hall resistance measurement. Both the fieldlike and dampinglike effective fields are extracted from a single measurement using the derived fitting functions for the second harmonic Hall resistance. The first harmonic Hall resistance acts as a reference to confirm that the experimental parameters are consistent with the derived equations.

/pdf/simultaneous-determination-of-effective-spin-orbit-torque-3k5j6iqyy3.pdf

Simultaneous determination of effective spin-orbit torque fields in magnetic structures with in-plane anisotropy

The ability to make devices that mimic the human brain has been a subject of great interest in scientific research in recent years. Current artificial intelligence algorithms are primarily executed on the von Neumann hardware. This causes a bottleneck in processing speeds and is not energy efficient. In this work, we have demonstrated a synaptic element based on a magnetic domain wall device. The domain wall motion was controlled with the use of synthetic pinning sites, which were introduced by boron (B+) ion-implantation for local modification of the magnetic properties. The magnetization switching process of a Co/Pd multilayer structure with perpendicular magnetic anisotropy was observed by using MagVision Kerr microscopy system. The B+ implantation depth was controlled by varying the thickness of a Ta overcoat layer. The Kerr microscopy results correlate with the electrical measurements of the wire which show multiple resistive states. The control of the domain wall motion with the synthetic pinning sites is demonstrated to be a reliable technique for neuromorphic applications.

/pdf/synaptic-element-for-neuromorphic-computing-using-a-magnetic-3m813htcxd.pdf

Synaptic element for neuromorphic computing using a magnetic domain wall device with synthetic pinning sites

High temperature studies of spin Hall effect have often been neglected despite its profound significance in real-world devices. In this work, high temperature spin torque ferromagnetic resonance measurement was performed to evaluate the effects of temperature on the Gilbert damping and spin Hall efficiency of PtxCu1−x. When the temperature was varied from 300 K to 407 K, the Gilbert damping was relatively stable with a change of 4% at composition x = 66%. Alloying Pt and Cu improved the spin Hall efficiency of Pt75Cu25/Co/Ta by 29% to a value of 0.31 ± 0.03 at 407 K. However, the critical switching current density is dependent on the ratio between the Gilbert damping and spin Hall efficiency and the smallest value was observed when x = 47%. It was found that at this concentration, the spin transparency was at its highest at 0.85 ± 0.09 hence indicating the importance of interfacial transparency for energy efficient devices at elevated temperature.

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Funan Tan

Papers

Oxide-based RRAM materials for neuromorphic computing

Bi-directional high speed domain wall motion in perpendicular magnetic anisotropy Co/Pt double stack structures

Simultaneous determination of effective spin-orbit torque fields in magnetic structures with in-plane anisotropy

Synaptic element for neuromorphic computing using a magnetic domain wall device with synthetic pinning sites

Thermal behavior of spin-current generation in Pt x Cu 1-x devices characterized through spin-torque ferromagnetic resonance