G
G. Kelner
Researcher at United States Naval Research Laboratory
Publications - 19
Citations - 548
G. Kelner is an academic researcher from United States Naval Research Laboratory. The author has contributed to research in topics: Ion implantation & Annealing (metallurgy). The author has an hindex of 11, co-authored 19 publications receiving 544 citations.
Papers
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Journal ArticleDOI
Al and B ion‐implantations in 6H‐ and 3C‐SiC
Mulpuri V. Rao,Peter Griffiths,O. W. Holland,G. Kelner,Jaime A. Freitas,David S. Simons,Peter H. Chi,Mario Ghezzo +7 more
TL;DR: In this paper, low-keV and high-meV energy Al and B implants were performed into n-type 6H and 3C-SiC at both room temperature and 850 °C.
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Phosphorus and boron implantation in 6H–SiC
Mulpuri V. Rao,Jason A. Gardner,Peter H. Chi,O. W. Holland,G. Kelner,James W. Kretchmer,Mario Ghezzo +6 more
TL;DR: In this paper, boron ion implantations were performed at various energies in the 50 keV-4 MeV range and range statistics of P+ and B+ were established by analyzing the as-implanted secondary ion mass spectrometry depth profiles.
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β-SiC MESFET's and buried-gate JFET's
TL;DR: In this paper, β-SiC MESFET and buried-gate JFET structures have been fabricated and evaluated using chemical vapor deposition on a p-type SiC layer.
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PN junction formation in 6HSiC by acceptor implantation into n-type substrate
Mulpuri V. Rao,Jason A. Gardner,Peter Griffiths,O. W. Holland,G. Kelner,Peter H. Chi,David S. Simons +6 more
TL;DR: A1 and B implantations were performed into n-type 6H-bulk SiC and epitaxial layers at both room temperature and 850°C as mentioned in this paper, and Annealings were performed in the temperature range of 1100-1650°C in a SiC crucible.
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High-transconductance beta -SiC buried-gate JFETs
TL;DR: In this paper, an improved performance buried-gate SiC junction field effect transistor (JFET) has been fabricated and evaluated, which uses an n-type beta -SiC film epitaxially grown by chemical vapor deposition on the Si(0001) face of a p-type 6H alpha-SiC single crystal.