Plasma-assisted atomic layer deposition (ALD) is an energy-enhanced method for the synthesis of ultra-thin films with A-level resolution in which a plasma is employed during one step of the cyclic deposition process. The use of plasma species as reactants allows for more freedom in processing conditions and for a wider range of material properties compared with the conventional thermally-driven ALD method. Due to the continuous miniaturization in the microelectronics industry and the increasing relevance of ultra-thin films in many other applications, the deposition method has rapidly gained popularity in recent years, as is apparent from the increased number of articles published on the topic and plasma-assisted ALD reactors installed. To address the main differences between plasma-assisted ALD and thermal ALD, some basic aspects related to processing plasmas are presented in this review article. The plasma species and their role in the surface chemistry are addressed and different equipment configurations, including radical-enhanced ALD, direct plasma ALD, and remote plasma ALD, are described. The benefits and challenges provided by the use of a plasma step are presented and it is shown that the use of a plasma leads to a wider choice in material properties, substrate temperature, choice of precursors, and processing conditions, but that the processing can also be compromised by reduced film conformality and plasma damage. Finally, several reported emerging applications of plasma-assisted ALD are reviewed. It is expected that the merits offered by plasma-assisted ALD will further increase the interest of equipment manufacturers for developing industrial-scale deposition configurations such that the method will find its use in several manufacturing applications.

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Plasma-Assisted Atomic Layer Deposition: Basics, Opportunities, and Challenges

Applications of atomic layer deposition to nanofabrication and emerging nanodevices

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

Review on high-k dielectrics reliability issues

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

Dielectric breakdown mechanisms in gate oxides

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.

Origin of the threshold voltage instability in SiO 2 /HfO 2 dual layer gate dielectrics

The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.

Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

An approach to the application of the charge pumping technique is proposed as a tool for the measurement of interface trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the interface-trap distribution is slowly varying with energy and that the trap capture cross section is nearly constant over energy and temperature. >

Spectroscopic charge pumping: A new procedure for measuring interface trap distributions on MOS transistors

The total safe operating area (SOA) of LDMOS transistors is discussed. It is shown that the transistors are subjected to different kinds of stresses, yielding a combination of electrical and thermal degradation and/or failure modes. A methodology to build the total SOA for LDMOS transistors is highlighted and is experimentally verified on a 40-V LDMOS implemented in a

Characterization of Total Safe Operating Area of Lateral DMOS Transistors

The generation of fast interface traps due to channel hot-carrier injection in n-channel MOS transistors is investigated as a function of stress temperature. The relative importance of the mechanisms for the generation of fast interface traps by hot electrons and hot holes is shown to be independent of the temperature. In all cases the generation of fast interface traps is slightly reduced at lower temperatures. The degradation of transistor I/sub d/-V/sub g/ characteristics, on the other hand, is strongly enhanced at lower temperatures. This is explained by a previously suggested model on the temperature dependence of the influence of the local narrow potential barrier, induced at the drain junction as a result of degradation, on the reverse-mode current characteristics. It is shown that only a minor part of the large current reduction at low temperatures can be ascribed to enhanced electron trapping. >

Temperature dependence of the channel hot-carrier degradation of n-channel MOSFET's

A simple method of unambiguously determining the presence of any geometric component in a charge-pumping measurement by collecting this component at another node via a nearby junction is presented. With the method it has been possible to study the dependence of geometric components on device dimensions and various experimental conditions with unprecedented sensitivity. By effectively separating the two current contributions, this method can at the same time be used to reduce geometric components in the regular charge-pumping signal, thereby increasing the accuracy of the various implementations of the charge pumping (CP) technique. >

G. Van den bosch

Papers

Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

Spectroscopic charge pumping: A new procedure for measuring interface trap distributions on MOS transistors

Characterization of Total Safe Operating Area of Lateral DMOS Transistors

Temperature dependence of the channel hot-carrier degradation of n-channel MOSFET's

On the geometric component of charge-pumping current in MOSFETs