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Girish Pahwa
Researcher at University of California, Berkeley
Publications - 51
Citations - 1048
Girish Pahwa is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Negative impedance converter & Capacitance. The author has an hindex of 13, co-authored 36 publications receiving 615 citations. Previous affiliations of Girish Pahwa include Indian Institutes of Technology & Indian Institute of Technology Kanpur.
Papers
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Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description
Girish Pahwa,Tapas Dutta,Amit Agarwal,Sourabh Khandelwal,Sayeef Salahuddin,Chenming Hu,Yogesh Singh Chauhan +6 more
TL;DR: An accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications and accurately captures different aspects of NCFET is presented.
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Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Above-Threshold Behavior
TL;DR: In this paper, the authors analyzed the impact of length scaling on the ON-state operation of the two classes of double-gate negative capacitance transistors: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal- ferroelectric -insulator-, semiconductor(MFIS).
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Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures
TL;DR: In this paper, a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures, namely metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-FERO-INSIS (MFIS), is presented.
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Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure
TL;DR: In this article, a physics-based compact model for a ferroelectric negative capacitance FET with a metal-ferroelectric-insulator-semiconductor (MFIS) structure is presented.
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Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM
Tapas Dutta,Girish Pahwa,Amit Ranjan Trivedi,Saurabh Sinha,Amit Agarwal,Yogesh Singh Chauhan +5 more
TL;DR: It is demonstrated that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.