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Electronic Transport In Mesoscopic Systems

There can be little doubt that the Monte Carlo method for semiconductor device simulation has enormous power as a research tool. It represents a detailed physical model of the semiconductor material(s), and provides a high degree of insight into the microscopic transport processes. However, if the authority ascribed to Monte Carlo models of devices at 1/spl mu/m feature size is to be maintained for devices below O.1/spl mu/m, modelling of the fundamental physics must be further improved. And if the Monte Carlo method is to be successful as a semiconductor device design tool, the device model must be made more realistic. Success in the industrial sector depends on this, but also on achieving fast run-times optimisation - where the scope and need for ingenuity is now greatest.

The Monte Carlo method for semiconductor device simulation

We have produced ultrathin epitaxial graphite films which show remarkable 2D electron gas (2DEG) behavior. The films, composed of typically 3 graphene sheets, were grown by thermal decomposition on the (0001) surface of 6H-SiC, and characterized by surface-science techniques. The low-temperature conductance spans a range of localization regimes according to the structural state (square resistance 1.5 kOhm to 225 kOhm at 4 K, with positive magnetoconductance). Low resistance samples show characteristics of weak-localization in two dimensions, from which we estimate elastic and inelastic mean free paths. At low field, the Hall resistance is linear up to 4.5 T, which is well-explained by n-type carriers of density 10^{12} cm^{-2} per graphene sheet. The most highly-ordered sample exhibits Shubnikov - de Haas oscillations which correspond to nonlinearities observed in the Hall resistance, indicating a potential new quantum Hall system. We show that the high-mobility films can be patterned via conventional lithographic techniques, and we demonstrate modulation of the film conductance using a top-gate electrode. These key elements suggest electronic device applications based on nano-patterned epitaxial graphene (NPEG), with the potential for large-scale integration.

Ultrathin epitaxial graphite: 2D electron gas properties and a route toward graphene-based nanoelectronics

The capacitor is a key element of electronic devices and is characterized by positive capacitance. However, a negative capacitance (NC) behaviour may occur in certain cases and implies a local voltage drop opposed to the overall applied bias. Therefore, a local NC response results in voltage enhancement across the rest of the circuit. Within a suitably designed heterostructure, ferroelectrics display such an NC effect, and various ferroelectric-based microelectronic and nanoelectronic devices have been developed, showing improved performance attributed to NC. However, the exact physical nature of the NC response and direct experimental evidence remain elusive or controversial thus far. In this Review, we discuss the physical mechanisms responsible for ferroelectric NC, tackling static and transient NC responses. We examine ferroelectric responses to voltage and charge, as well as ferroelectric switching, and discuss proof-of-concept experiments and possibilities for device implementation. Finally, we highlight different approaches for the optimization of the intrinsic NC response to maximize voltage amplification. Ferroelectrics-based materials can display a negative capacitance (NC) effect, providing an opportunity to implement NC in electronic circuits to improve their performance. In this Review, the authors discuss static and transient NC responses in ferroelectrics and highlight proof-of-concept experiments and possibilities for device implementation.

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Ferroelectric negative capacitance

Negative capacitance (NC) FETs with channel lengths from 30 nm to $50~\mu \text{m}$ , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation.

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

We present a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS). A new segmentation approach is proposed to simulate MFIS NCFET, which correctly takes care of the nonuniformity in potential and horizontal electric field at the ferroelectric–oxide interface. We show that MFMIS NCFET provides a higher ON-current than MFIS NCFET except for the ferroelectrics with very low remnant polarization ( ${P}_{r}$ ) in the high operating voltage regime. We find that this behavior is caused by a reduction or enhancement of the longitudinal electric field in the channel of MFIS structure depending upon ${P}_{r}$ of the ferroelectric and the operating voltage. Moreover, there exists an optimum ${P}_{r}$ which provides maximum ON-current for both the devices. We also find that MFIS NCFET is more prone to hysteresis and starts showing a hysteretic behavior at a lower ferroelectric thickness compared with MFMIS NCFET.

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal–ferroelectric–insulator–semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal–ferroelectric–metal–insulator–semiconductor structure.

Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure

We compare the performance of static random access memory (SRAM) cells based on negative capacitance (NC) FinFETs and reference FinFETs at the 7-nm technology node. We use a physics-based model for NC FinFETswhere we couple the Landau–Khalatnikovmodel of ferroelectric materials with the standard BSIM-CMG model of FinFET. For the reference FinFETs, we use the predictive model parameters optimized for SRAM design as per the ASAP7 PDK. We exploit the unique characteristics of NC-FinFETs and demonstrate that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.

Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM

We have developed a physics based model for negative capacitance (NC) FinFETs by coupling the Landau-Khalatnikov model of ferroelctric materials with the standard BSIM-CMG model of FinFET. We apply our model to thin film Y-HfO 2 (yttrium-doped hafnium oxide) based NC-FinFETs designed using state of the art 22nm technology node FinFETs. Using the same ferroelectric material, we demonstrate a device design that can match the I ON of the 22nm technology node at 50% reduced V DD with a simultaneous I OFF improvement of ≈ 83%. Further, we analyze the impact of variation of ferroelectric properties, remnant polarization (P r ) and coercive electric field (E c ) on the device figures of merit which can lay a very useful guideline towards investigation of new ferroelectric materials for NC-FinFET. We investigate the impact of scaling the ferroelectric thickness on the electrical characteristics of NC-FinFET. We critically examine an interesting phenomenon of “negative DIBL” which leads to reduced off-current (I OFF ), increased threshold voltage (V th ), yet increased on-current (I ON ) at higher drain biases. This effect gets pronounced with increasing ferroelectric thickness. Finally, we compare the logic figures of merit of the NC-FinFET with those of the reference FinFET.

Tapas Dutta

Papers

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

Compact Model for Ferroelectric Negative Capacitance Transistor With MFIS Structure

Performance Evaluation of 7-nm Node Negative Capacitance FinFET-Based SRAM

Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X I ON using compact modeling approach