Hien Minh Le

TL;DR: In this article, a system and a method for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains is presented.

TL;DR: A single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on- chip word-line voltage supply generation, a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, and on-chip OTPROM programming voltage generation, clock generation and distribution are described.

TL;DR: In this paper, a victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit by a lateral castout (LCO) command.

TL;DR: In this paper, the authors describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation, a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control.

TL;DR: In this paper, the authors propose a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of an electronic component design into electronic test equipment employed during validation testing of the actual electronic component.