Circuit techniques for enabling a sub-0.9 V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes Read Word-line (RWL) preferential boosting to increase read margin and improve data retention time. Read speed is enhanced with a hybrid current/voltage sense amplifier that allows the Read Bit-line (RBL) to remain close to VDD. A regulated bit-line write scheme for driving the Write Bit-line (WBL) is equipped with a steady-state storage node voltage monitor to overcome the data `1' write disturbance problem of the PMOS gain cell without introducing another boosted supply for the Write Word-line (WWL) over-drive. An adaptive and die-to-die adjustable read reference bias generator is proposed to cope with PVT variations. Monte Carlo simulations compare the 6-sigma read and write performance of proposed eDRAM against conventional designs. Measurement results from a 64 kb eDRAM test chip implemented in a 65 nm low-leakage CMOS process show a 1.25 ms data retention time with a 2 ns random cycle time at 0.9 V, 85°C, and a 91.3 μW per Mb static power dissipation at 1.0 V, 85°C.

A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches

Circuit techniques for enhancing the retention time and random cycle of logic-compatible embedded DRAMs (eDRAMs) are presented. An asymmetric 2T gain cell utilizes the gate and junction leakages of a PMOS write device to maintain a high data `1' voltage level which enables fast read access using an NMOS read device. A current-mode sense amplifier (C-S/A) featuring a cross-coupled PMOS latch and pseudo-PMOS diode pairs is proposed to overcome the innate problem of small read bit-line (RBL) voltage swing in 2T eDRAMs with improved voltage headroom and better impedance matching under process-voltage-temperature (PVT) variations. A half-swing write bit-line (WBL) scheme is adopted to improve the WBL speed by 33% and reduce its power dissipation by 25% during write-back operation with no effect on retention time. A stepped write word-line (WWL) driver reduces the current drawn from the boosted high and low supplies by 67%. A 192 kb eDRAM test chip with 512 cells-per-BL implemented in a 65 nm low-power (LP) CMOS process shows a random cycle frequency and latency of 667 MHz and 1.65 ns, respectively, at 1.1 V and 85 × °C. The measured refresh period at a 99.9% bit yield condition was 110 μs which is comparable to that of recently published 1T1C eDRAM designs.

A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches

The majority of the power consumption of a high-throughput LDPC decoder is spent on memory. Unlike in a general-purpose processor, the memory access in an LDPC decoder is deterministic and the access window is short. We take advantage of the unique memory access characteristic to design a non-refresh eDRAM that holds data for the necessary access window, and further improve its access time by trading off the excess retention time. The resulting 3T eDRAM cell is designed to balance wordline coupling to reliably retain data for a fast access. We integrate 32 5x210 non-refresh eDRAM arrays in a row-parallel LDPC decoder suitable for the IEEE 802.11ad standard. Memory refresh is eliminated and random access is replaced with a simple sequential addressing. With row merging and dual-frame processing, the 1.6 mm 2 65 nm LDPC decoder chip achieves a peak throughput of 9 Gb/s at 89.5 pJ/b, of which only 21% is spent on eDRAMs. With voltage and frequency scaling, the power consumption of the LDPC decoder is reduced to 37.7 mW for a 1.5 Gb/s throughput at 35.6 pJ/b.

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

An emerging data-center market merges network and server attributes into a single wire-speed processor SoC. These processors are not network endpoints that consume data, but inline processors that filter or modify data and send it on. Wire-speed processors merge attributes from 1) network processors: many threaded low power cores, accelerators, integrated network and memory I/O, smaller memory line sizes and low total power, and from 2) server processors: full ISA cores, standard programming models, OS and hypervisor support, full virtualization and server RAS & infrastructure. Typical applications are edge-of-network processing, intelligent I/O devices in servers, network attached appliances, distributed computing, and streaming applications.

A wire-speed power TM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads

A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. The macro employs a 6 transistor micro sense-amplifier architecture with extended precharge scheme to enhance the sensing margin for product quality. The detailed study shows a 67% bit-line power reduction with only 1.7% area overhead, while improving a read zero margin by more than 500ps. The array voltage window is improved by the programmable BL voltage generator, allowing the embedded DRAM to operate reliably without constraining of the microprocessor voltage supply windows. The 2.5nm gate oxide transistor cell with deep-trench capacitor is accessed by the 1.7 V wordline high voltage (VPP) with V WL low voltage (VWL), and both are generated internally within the microprocessor. This results in a 32 MB on-chip L3 on-chip-cache for 8 cores in a 567 mm POWER7™ die.

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distribution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a programmable pipeline, achieving 1.8 ns latency, and features concurrent refresh capability.

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation, a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distribution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a programmable pipeline, achieving 1.8 ns latency, and features concurrent refresh capability.

Pamela Wilcox

Papers

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS