Jethro C. Law

TL;DR: In this article, a virtual power-gated cell (VPC) is configured with control circuitry for buffering control signals and a powergated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFET for virtual positive rail nodes, which can propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input.

TL;DR: A single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on- chip word-line voltage supply generation, a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, and on-chip OTPROM programming voltage generation, clock generation and distribution are described.

TL;DR: In this article, a phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated is presented.

TL;DR: In this paper, the authors describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation, a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control.

TL;DR: In this article, a front-end logic circuit with a latch and a limited switch dynamic logic gate has been proposed to generate a modified clock signal in response to receiving a clock signal from a clock source, and the clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.