This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Due to the severe cost pressure of consumer electronics, a migration to an advanced nanoscale CMOS processes, which is primarily developed for fast and low-power digital circuits operating at low supply voltages, is necessary, but it forces wireless RF transceivers to exploit more and more digital circuitry These basic CMOS properties tend to coerce the design of wireless functions towards the digital domain where transistors are utilized as switches rather than current sources Within the past decade, there have been tremendous efforts towards implementing fully-digital or digitally-intensive RF transmitters in which they demonstrate transmitter designs that operate from baseband up to the pre-power amplifier (PA) stage entirely in the digital domain In view of this digitalization, the RF transmitter modulator, being the nearest to the antenna as it converts digital baseband modulation samples into an RF waveform, is considered the most critical building block of the transmitter, and it can be in the form of either a polar, Cartesian (I/Q), or an outphasing topology For wide modulation bandwidths, due to their direct linear summation of the in-phase (I) and quadrature-phase (Q) signals and thus the avoidance of the bandwidth expansion, Cartesian modulators are substantiated as the most appropriate choice over their polar or outphasing counterparts Since the effective modulating sample resolution is the utmost important parameter as it directly impacts the achievable dynamic range, linearity, error vector magnitude (EVM), noise floor, and out-of-band spectral emission, this thesis proposes a wideband, high-resolution, all-digital orthogonal I/Q radio-frequency digital-to-analog (RF-DAC) Chapter 1 briefly provides an overview of the conventional RF radio building blocks It is discussed that contemporary RF transceivers must support most of multi-mode/multiband communication standards such as Wi-Fi, Bluetooth, and Fourth Generation (4G) of 3GPP cellular In Chapter 2, four types of RF transmitter architectures have been briefly described The analog I/Q modulators are the most straightforward and widely employed RF transmitters They are later replaced by analog polar counterparts to address their poor power efficiency and noise performance On the other hand, in the analog polar RF transmitters, their related amplitude and phase signals must be aligned or spectral regrowth is inevitable Utilizing digitally intensive polar RF transmitters mitigates the latter alignment issue Nonetheless, polar transmitters suffer from an additional issue that is related to their nonlinear conversion of in-phase and quadrature-phase signals into the amplitude and phase representation Therefore, the polar RF transmitters are not able to manage very large baseband bandwidth of the most stringent communication standards, therefore, reusing I/Q modulators based on digitally intensive implementation appears to be a reasonable approach to resolve this issue The digital I/Q RF transmitters, however, suffer again from inadequate power efficiency Moreover, the combination of in-phase and quadrature phase paths must be orthogonal to produce an undistorted-upconverted-modulated RF signal In Chapter 3, a novel all-digital I/Q RF modulator is described Employing an upconverting RF clock with a 25% duty cycle ensures the orthogonal summation of Ipath and Qpath, which avoids nonlinear signal distortion It was clarified that electric summing of I and Q digital unit array switches is the most appropriate I/Q orthogonal summation approach Moreover, to address all four quadrants of the constellation diagram, the differential quadrature upconverting RF clocks must be utilized In addition, it was explained that employing switches instead of utilizing current sources leads to superior noise performance of the all-digital I/Q transmitter In Chapter 4, a novel 2×3-bit all-digital I/Q (Cartesian) RF transmit modulator is implemented which operates as an RF-DAC The modulator performs based on the concept of orthogonal summing, which is introduced and elaborated in Chapter 3 It is based on a time-division duplexing (TDD) manner of an orthogonal I/Q addition By employing this method, a very simple and compact design featuring high-output power, power-efficiency and low-EVM has been realized The resolution of the experimental RF-DAC presented in this work is only 3-bit (including one sign bit), but it will be demonstrated in the following chapters that the resolution can be increased to 8–12 bits in an unequivocal manner for utilization in multi-standard wireless applications In Chapter 5, the system design considerations of the proposed high-resolution, wideband all-digital I/Q RF-DAC are discussed It is demonstrated that the upsampling clock frequency (fCKR), DRAC resolution (Nb), and memory length (lmem) are three important parameters that affect the dynamic performance of the proposed RF-DAC Based on system level simulation results and the limitation in implementing the RF-DAC test-chip, they are designated as fCKR=300 MHz, Nb=12 bit, and lmem=8 k-word The effect of these parameters on the in-band as well as out-of-band performance of RF-DAC are investigated It is concluded that exploiting 13 bits of resolution for quadrature baseband signals is sufficient to meet the most stringent communication requirements In Chapter 6, the theory and the design procedure of an innovative, differential, orthogonal power combining network, which is employed in the proposed all-digital modulator, is thoroughly explained It is demonstrated that, in order to maintain an orthogonal operation between the in-phase and quadrature-phase paths, the effect of the power combiner on the in-phase and quadrature-phase paths must be considered, otherwise, the linear summation will not occur As a result, the EVM and linearity performance will diminish The power combiner consists of a transformer balun as well as its related programmable primary and secondary shunt capacitors In order to achieve high efficiency at full power of operation, a class-E type matching network is adopted and subsequently modified in order to obtain a minimum modulation error A switchable cascode structure is exploited to mitigate a reliability issue as well as to perform a mixer operation Moreover, utilizing a switchable cascode structure also improves the isolation between quadrature paths Furthermore, it is explained that the power combiner efficiency is primarily related to the transformer balun efficiency A procedure is introduced in order to design an efficient, compact balun transformer Also, it is explained that the RF-DAC operates as a class-B power amplifier at the power back-off levels As a result, its performance in the power back-off region is lowered In Chapter 7, the implemented wideband, 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65-nm CMOS is presented Employing the orthogonal I/Q combining approach which is proposed in Chapter 3 guarantees the isolation between in-phase and quadrature-phase paths The 4×f0 off-chip single-ended clock is converted to a differential version employing an on-chip transformer The wide swing, low phase noise, high-speed dividers are incorporated to translate the 4×f0 differential clock to the fundamental frequency of f0 In the meantime, the complementary quadrature sign bit is used to address four quadrants of the related constellation diagram The 25% differential quadrature clocks are generated using logic-AND operation between 2×f0 differential clock and f0 differential quadrature clocks The 12-bit DRAC is implemented employing a segmentation approach, which consists of 256 MSB and 16 LSB thermometer unit cells The layout arrangement of the DRAC unit cell proves to be very crucial It was concluded that the vertical layout would be the most appropriate selection The LO leakage and I/Q image rejection technique as well as two DPD memoryless techniques of AM-AM/AM-PM and constellation mapping are introduced, which will be extensively utilized in the measurement segment In Chapter 8, the high-resolution wideband 2×13-bit all-digital I/Q transmitter, which was introduced in Chapter 7, is thoroughly measured First, the chip is tested in continuouswave mode operation It is demonstrated that, with a 13V supply and, of course, an on-chip power combiner, the RF-DAC chip generates more than 21dBm RF output power within a frequency range of 136–251 GHz The peak RF output power, overall system, and drain energy efficiencies of the modulator are 228 dBm, 34%, and 42%, respectively The measured static noise floor is below -160 dBc/Hz The digital I/Q RF modulator demonstrates an IQ image rejection and LO leakage of -65 dBc and -68 dBc, respectively The RF-DAC could be linearized employing either of the two digital predistortion (DPD) approaches: memoryless polynomial or a lookup table Its linearity is examined utilizing 4/16/64/256/1024-QAM baseband signals while their related modulation bandwidth can be as high as 154 MHz Using AM-AM/AM-PM DPD improves the linearity by more than 25 dB while the measured EVM is better than -28 dB Moreover, the constellation-mapping DPD is applied to the RF-DAC which improves linearity by more than 19 dB These numbers indicate that this innovative concept is a viable option for the next generations of multi band/multi-standard transmitters The realized demonstrator can perform as an energy-efficient RF-DAC in a stand-alone digital transmitter directly (eg, for WLAN) or as a pre-driver for high-power basestation PAs Chapter 9 draws the conclusions of the this thesis work and provides recommendations for future research and directions in the field of all-digital RF transmitters for wireless communication applications

All-Digital I/Q RF-DAC

Two high selectivity fifth-order wideband bandpass filters (BPFs) with multiple transmission zeros based on transversal signal-interaction concepts are proposed in this paper. Two transmission paths consisting of a shorted stub and two open coupled lines are used to realize signal transmission from Port 1 to Port 2. Two fifth-order wideband passbands with six and ten transmission zeros from 0 GHz to 2f0 (f0 is center frequency of the passband) can be achieved respectively due to the superposition of signals of the two transmission paths. Two prototypes with 3-dB fractional bandwidths of 61.7% (2.07-3.92 GHz) and 48.2% (2.3-3.76 GHz) are designed and fabricated for demonstration. Good agreement can be observed between simulated and measured performances.

High Selectivity Fifth-Order Wideband Bandpass Filters With Multiple Transmission Zeros Based on Transversal Signal-Interaction Concepts

A new type of microstrip dual-mode dual-band bandpass filter (BPF) using a single quadruple-mode resonator (QMR) is proposed in this paper. The classical even-/odd-mode method is applied to analyze the characteristics of the proposed resonator, which shows that it has two pairs of symmetrical resonant modes. Owing to the inherent characteristic of a dual-mode resonator and source-load coupling, four transmission zeros can be produced and these four resonant modes can be divided in two groups, resulting in a dual-band BPF with two resonant modes in each passband. As examples, two dual-mode dual-band BPFs, Filter A with central frequencies (CFs) at 1.99/5.58 GHz and -3-dB fractional bandwidth (FBW) of 62.3%/19.7%, while Filter B with CFs at 1.64/5.26 GHz and -3-dB FBW of 32.9%/7.6%, are designed and fabricated. An aperture-backed compensation technique is employed in such two filters to enhance the coupling strength between the feeding lines and QMR. Furthermore, a meander coupled-line section is employed in the Filter A design, while a defected microstrip structure is introduced in Filter B design, so as to increase much more design freedoms for tuning filter performance. The fabricated two filters exhibit simple design procedures, low insertion losses, good return losses, sharp shirts, and compact sizes. Moreover, two BPFs do not need external input/output impedance transformation feeding lines.

Compact and Sharp Skirts Microstrip Dual-Mode Dual-Band Bandpass Filter Using a Single Quadruple-Mode Resonator (QMR)

In this paper, compact ultra-wideband (UWB) bandpass filters with ultra-narrow dual- and quad-notched bands are proposed using the broadside-coupled microstrip/coplanar waveguide (CPW) structure. The multiple-modes UWB operation is obtained through the CPW detached-mode resonator (DMR) and broadside-coupled microstrip/CPW transition. To avoid the existing interferences such as the wireless local-area network signals (i.e., 5.2- and 5.8-GHz bands) in the UWB passband simultaneously, dual-notched bands can be finely employed and independently adjusted by the embedded quarter-wavelength (λ/4) CPW resonators and the λ/4 meander slot-line inserted in the DMR, respectively. To further cancel the interferences from the 3.5-GHz worldwide interoperability for microwave access and 6.8-GHz RF identification communication, the λ/4 meander defected microstrip structure is employed. Based on the structures mentioned above, a series of UWB bandpass filters with dual- and quad-notched bands are then designed and fabricated. With good passband/stopband performances, compact size, and low cost, the proposed filters are attractive for the practical applications.

Compact Ultra-Wideband (UWB) Bandpass Filter With Ultra-Narrow Dual- and Quad-Notched Bands

Compact dual-band bandpass filters (BPFs) are proposed using the novel embedded spiral resonators (ESRs) in this letter. Each ESR consists of two sets of spiral-lines embedded in a microstrip rectangular open-loop (MROP). The resonator has two functions in the filter: 1) dual-resonance operation mainly provided by the spiral-lines is employed to generate two passbands simultaneously. 2) MROP acting as the dual-feeding structure is introduced to achieve good input/output (I/O) coupling for both passbands. With proper tapping scheme, additional transmission zeros can be obtained to improve the passband selectivity. To verify the principle above, two dual-band BPFs are implemented. These filters with passbands operated at 2.4/5.2 GHz and 2.45/5.7 GHz can finely meet the wireless local area network (WLAN) bands requirements, respectively.

Compact Dual-Band Bandpass Filters Using Novel Embedded Spiral Resonator (ESR)

A wideband bandpass filter (WBPF) with excellent selectivity is proposed. An equivalent circuit model of the new complementary split-ring resonator (CSRR)-based resonator with good wideband response is presented. A WBPF with strong passband selectivity and wide stopband can be achieved by the new resonators with a proper coupled scheme using the eighth-wavelength (λ/8) directly coupled parallel microstrip-lines. Specifically, the filter exhibits a competitive attenuation slope of 262.2 and 75.9 dB/GHz in the lower and upper passband transitions, respectively.

Wideband bandpass filter with excellent selectivity using new CSRR-based resonator

In this paper, a 360° wideband phase shifter with current limited vector-sum and digital calibration is presented to achieve high phase resolution and low amplitude error. The output phase is synthesized from quadrature vectors by variable gain amplifiers (VGAs) with current-digital to analog converters (I-DACs). Several VGA control algorithms are investigated to find trade off among phase error, amplitude error, and power consumption. A current limited vector-sum method is proposed to achieve low phase error, amplitude error, and power consumption, simultaneously. Quadrant selection is realized by the reconfigurable VGAs without extra switch circuit. Coarse- and fine-scaling of quadrature vector amplitude is accomplished by I-DACs with segments of different current weights. The phase non-linearity is calibrated using digital pre-distortion to further improve the phase error. To verify the mechanism mentioned above, a fully integrated 10-bit phase shifter operating at 3–7 GHz with current limited vectors is implemented and fabricated in a conventional 40–nm CMOS technology. It exhibits root mean square (RMS) phase error of 0.41°–1.67°, RMS amplitude error of 0.42–0.89 dB, and effective phase resolution of 1.406° (8-bit) from 3–7 GHz. The core circuit occupies 0.19 mm2 and draws 11.4–16.2 mW from 1.1 V supply.

High-Resolution Wideband Phase Shifter With Current Limited Vector-Sum

In this article, a 22.9–38.2-GHz dual-path noise-canceling low noise amplifier (LNA) is proposed, which can achieve a low noise figure (NF) by reducing the noise of both paths. Such LNA consists of one common gate (CG) amplifier with one three-stage transformer, one resistive feedback common-source (CS) amplifier, and two amplitude-adjusting amplifiers. The three-stage transformer is used in the CG amplifier to provide gain-boosting, noise-reducing, and wideband inter-stage matching operation, simultaneously. Meanwhile, amplitude-adjusting amplifiers with reconfigurable phase-tuning lines are utilized in both paths to optimize the noise-canceling performance. To verify the aforementioned principle, a dual-path noise-canceling LNA is implemented and fabricated using a conventional 28-nm CMOS technology. The proposed LNA consumed 18.9 mW under a 0.9-V supply. The measured NF is 2.65–4.62 dB within the operating frequency range of 22.9–38.2 GHz, while the peak gain is 14.5 dB. The in-band input 1-dB compression point (IP1 dB) and input third-order intercept point (IIP3) are −13.2 to −6.6 and −3.6 to 3.2 dBm, respectively.

/pdf/a-22-9-38-2-ghz-dual-path-noise-canceling-lna-with-2-65-4-62-5bdhqd8owi.pdf

A 22.9–38.2-GHz Dual-Path Noise-Canceling LNA With 2.65–4.62-dB NF in 28-nm CMOS

In this paper, two types (i.e., type-A and type-B) of hybrid microstrip/defected ground structure (DGS) cells are proposed for passive circuit implementation with ultra-wide stopband. Both cells consist of the stepped-impedance DGS and embedded folded slotline on the ground, which could obtain the dual-resonances. In type-A cell, a microstrip T-stub on the top side is introduced, which can not only allocate a strong coupling to the DGS with slotline on the bottom side, but also act as the input/output port. To finely adjust the dual-resonances of the type-B cell, a grounded microstrip patch is used. Meanwhile, such compact cells could feature an ultra-wide upper stopband, due to their own slow-wave effect. Based on the aforementioned hybrid microstrip/DGS cells, two dual-band bandpass filters (BPFs) and a dual-band filtering power divider (FPD) are proposed and fabricated. Measured and simulated results are in a fairly-close agreement. Both dual-band BPFs exhibit the ultra-wide upper stopband, which extends up to 40 GHz with a high rejection level about 30 dB. Besides, the dual-band FPD has merits of more than 18.7 dB of in-band isolation and 28 dB stopband rejection levels up to 40 GHz.

/pdf/dual-band-bandpass-filter-and-filtering-power-divider-with-pp1orvhwse.pdf

Huizhen Jenny Qian

Papers

Compact Dual-Band Bandpass Filters Using Novel Embedded Spiral Resonator (ESR)

Wideband bandpass filter with excellent selectivity using new CSRR-based resonator

High-Resolution Wideband Phase Shifter With Current Limited Vector-Sum

A 22.9–38.2-GHz Dual-Path Noise-Canceling LNA With 2.65–4.62-dB NF in 28-nm CMOS

Dual-Band Bandpass Filter and Filtering Power Divider With Ultra-Wide Upper Stopband Using Hybrid Microstrip/DGS Dual-Resonance Cells