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Showing papers by "Iouliia Skliarova published in 2009"


Proceedings ArticleDOI
29 Sep 2009
TL;DR: The state of the art in reconfigurable hardware recursion implementation is presented and existing proposals are described, analyzed, and compared according to such criteria as level of parallelism supported, approach to concurrency, ease of use, availability of automated high-level synthesis tools, etc.
Abstract: Reconfigurable systems are widely used nowadays to increase performance of computationally intensive applications. There exist a lot of synthesis tools that automatically generate customized hardware circuits from specifications in both high-level and hardware description languages. However, such tools have a limited applicability because they are unable to handle recursive functions whereas it is known that recursion is a powerful problem-solving method widely used in computer science. Therefore a great deal of research effort is aimed at efficient implementation of recursion in reconfigurable hardware. This paper presents the state of the art in this area. The existing proposals are described, analyzed, and compared according to such criteria as level of parallelism supported, approach to concurrency, ease of use, availability of automated high-level synthesis tools, etc.

25 citations


Proceedings Article
02 Oct 2009
TL;DR: The paper describes a model, architecture, and functionality of a priority buffer, which receives an arbitrary sequence of instructions and outputs a new sequence ordered in accordance with the priorities of the instructions that have already been received.
Abstract: The paper describes a model, architecture, and functionality of a priority buffer, which receives an arbitrary sequence of instructions and outputs a new sequence ordered in accordance with the priorities of the instructions that have already been received. Any new incoming instruction changes the output sequence because it has to be accommodated in the buffer on the basis of its priority. It is shown that the desired functionality of the buffer can be described efficiently by the proposed parallel hierarchical algorithms involving recursion. The algorithms have been modeled in general-purpose software and implemented in hardware (in a commercially available FPGA). The results of experiments have shown that the buffer operates in strong conformity with the requirements and specification. The required memory is allocated and deallocated dynamically. The proposed buffer architecture is easily scalable, which enables a buffer of any size to be provided.

20 citations


13 Nov 2009
TL;DR: Functional simulation of the designed system for garage control providing for automatic parking of arriving cars and driving them to the garage exit on requests is presented in a virtual mode enabling the relevant results to be evaluated visually on a monitor screen without the need for an expensive physical environment.
Abstract: The paper describes a system for garage control providing for automatic parking of arriving cars and driving them to the garage exit on requests. The system is composed of two sub-systems that are directly linked for simulation purposes and communicate through a wireless interface needed for physical implementation. One of the basic modules providing for management and priority-driven selection of parking slots is considered in detail. The complete system prototype was designed, implemented in FPGA, validated, and tested. Functional simulation of the designed system is presented in a virtual mode enabling the relevant results to be evaluated visually on a monitor screen without the need for an expensive physical environment.

15 citations


Proceedings ArticleDOI
28 Dec 2009
TL;DR: The paper argues importance of reconfigurable systems in education and suggests a multimedia tool augmented with an FPGA-based prototyping system, which could contribute to productive teaching of reconfigured computing.
Abstract: This paper proposes a method for efficient teaching of reconfigurable computing. Nowadays, reconfigurable systems, in general, and FPGA (Field-Programmable Gate Array) based systems, in particular, constitute an essential part of engineering practice. The paper argues importance of reconfigurable systems in education and suggests a multimedia tool augmented with an FPGA-based prototyping system, which could contribute to productive teaching of reconfigurable computing.

5 citations


Proceedings ArticleDOI
28 Dec 2009
TL;DR: The paper describes a computational system that is composed of a special-purpose processor augmented by an application-targeted coprocessor with variable instruction set that is to form the processor architecture in such a way that is the most appropriate to a selected scope of applications.
Abstract: The paper describes a computational system that is composed of a special-purpose processor augmented by an application-targeted coprocessor with variable instruction set. The primary objective is to form the processor architecture in such a way that is the most appropriate to a selected scope of applications and to optimize instructions of the coprocessor for a particular application. As an example the scope of combinatorial search algorithms was examined and experiments were carried out and analyzed with the relevant system implemented in FPGAs.

4 citations


13 Nov 2009
TL;DR: The paper suggests the methodology for validation of designed systems and experiments through the use of the developed simulation tools and interactive models on the basis of virtual visual samples imitating interacting physical objects.
Abstract: The paper suggests the methodology for validation of designed systems and experiments through the use of the developed simulation tools and interactive models. The primary idea is prototyping on the basis of virtual visual samples imitating interacting physical objects. The desired electronic functionality is implemented in reconfigurable hardware and, therefore, can easily be changed, which significantly simplifies such problems as verification of alternative implementations and eliminating potential errors. The desired physical functionality is modeled through observation of and experiences with interacting images which look like physical objects. The proposed methodology is very helpful and effective for many practical applications, such as mechanical systems control, robotics, process automation, transportation systems, computational devices, etc.

1 citations


Proceedings Article
02 Oct 2009
TL;DR: The paper presents a graphical specification of parallel hierarchical algorithms, suggests architecture of a parallel reconfigurable controller, indicates limitations and describes a formal method of synthesis allowing the given algorithms to be implemented in hardware on the basis of the proposed architecture.
Abstract: Many practical algorithms require support for hierarchy and parallelism. Hierarchy assumes an opportunity to activate one sub-algorithm from another and parallelism enables different sub-algorithms to be executed at the same time. The paper presents a graphical specification of parallel hierarchical algorithms, suggests architecture of a parallel reconfigurable controller, indicates limitations and describes a formal method of synthesis allowing the given algorithms to be implemented in hardware on the basis of the proposed architecture.