There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

To study the operational behaviour of λ-terms, we will use the denotational (mathematical) approach. A denotational semantics for a language is based on the choice of a space of semantics values, or denotations, where terms are to be interpreted. Choosing a space with nice mathematical properties can help in proving the semantic properties of terms, since to this aim standard mathematical techniques can be used.

λ Δ -Models

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

This chapter gives an overview of the design techniques based on hierarchical and parallel specifications First, hierarchical graph-schemes (HGSs) are introduced that enable complex digital control algorithms to be decomposed and described efficiently A module, described by an HGS, is the fundamental entity that provides the basis for the technique, and is an autonomous, complete, and potentially reusable component A module has to be designed such that: (1) it can be verified independently of other modules; (2) it possesses a well-defined external interface so it can be reused in different specifications It is shown that a set of HGSs (modules) can be implemented in a hierarchical finite state machine (HFSM) with stack memory Many VHDL examples are given that demonstrate that HFSMs permit the execution of hierarchical algorithms and provide support for recursion if required Various types of HFSMs are described and synthesizable VHDL templates for these are given that can be customized for particular problems Parallel specifications and parallel HFSMs are also discussed Many fully functioning VHDL examples for all the types of HFSMs above are presented and evaluated It is also shown how software programs can be mapped to hardware with the aid of HFSM models Finally, a variety of HFSM optimization techniques are proposed

Design Technique Based on Hierarchical and Parallel Specifications

Complex combinatorial problems appear in various systems providing real time processing. The majority of combinatorial problems that have to be solved are NP-complete and it limits the use of the respective mathematical models, methods and algorithms for a number of practical applications, for instance, for reactive embedded systems. The paper suggests architecture of hardware accelerator for combinatorial computations and a strategy of such computations based on a reconfigurable hardware/software (RHS) model. The resulting hardware has been implemented on the basis of XCV812E Virtex FPGA, and it can be reused for different combinatorial problems. The complexity of the FPGA allows implementing whole systems that include the proposed accelerator linked to a host application-specific embedded controller for real time processing. The paper presents and analyzes a set of experiments with the proposed accelerator on the base of three well-known combinatorial problems that are a Boolean satisfiability (SAT), a traveling salesman problem (TSP) and a covering problem. The results have shown that the proposed architecture together with the respective methods and algorithms allow to reduce the time of computations significantly.

Reconfigurable Combinatorial Accelerators for Real Time Processing

The existing trends and growing tendency to high-performance computing strongly require traditional computational algorithms to be revised in such a way that would permit optimal hardware implementations to be found. The latter can be done if algorithms can efficiently be mapped to hardware-specific functional blocks that require different style of thinking and manipulation by different operations and memory models. Besides, concurrency (pipelining and parallelism) can be widely applied. This paper focuses on data processing algorithms that use values of incoming data items as memory addresses with one-bit flags indicating presence or absence of data. The main problem of similar known methods is an appearance of huge number of memory cells with no data items (empty holes), which, nevertheless, have to be processed involving lots of unnecessary time. It is proposed to apply N-ary tree technique that enables data items to be stored and found very fast through executing special traversal procedure. Such trees completely differ from known tree-walk tables because they have pre-established configuration that does not require explicit addresses of subsequent (child) nodes. As a result the size of memory needed to keep data items is decreased in number of times. Finally, significantly more complicated problems can be solved faster and with smaller hardware resources. The presented results of numerous experiments clearly demonstrate advantages of the proposed method compared to known implementations.

Address-based data processing over N-ary trees

This chapter introduces FPGA architectures by presenting the general structure of modern devices and explaining the core elements and the most important embedded blocks, such as memory and digital signal processing slices. A few typical FPGA-based design scenarios are discussed that cover the phases of specification, supplying physical constraints, implementation, configuration and finally, testing. In this introductory chapter, design specifications are presented at the schematic level, where a circuit is constructed either from components available in vendor-specific libraries, user-defined blocks, or from properly customized intellectual property cores. A number of simple examples are given that are ready to be tested in FPGA-based prototyping boards. The three prototyping boards used in the book are characterized briefly and the general ideas for interaction with circuits and systems implemented in FPGAs are introduced. All the processing steps are explained through numerous examples.

FPGA Architectures, Reconfigurable Fabric, Embedded Blocks and Design Tools

Chapter deals with design of Moore FSMs based on using embedded memory blocks (EMB). The methods of trivial EMB-based implementation of logic circuits of both Moore and Mealy FSMs are discussed. In this case, only one EMB is enough for implementing the circuit. Next, the optimization methods are discussed based on replacement of logical conditions as well as encoding of the collections of microoperations. The considered methods are based on encoding the rows of FSM’s structure table. All these methods lead to two-level models of Mealy FSMs and to three-level models of Moore FSMs. Next, these methods are combined together for further optimizing the hardware amount in FSM logic circuits. The last section considers applying PES-based methods in EMB-based Moore FSMs. All discussed methods are illustrated by examples. The chapter is written together with PhD Malgorzata Kolopienczyk (University of Zielona Gora, Poland).

Iouliia Skliarova

Papers

Design Technique Based on Hierarchical and Parallel Specifications

Reconfigurable Combinatorial Accelerators for Real Time Processing

Address-based data processing over N-ary trees

FPGA Architectures, Reconfigurable Fabric, Embedded Blocks and Design Tools

Design of FSMs with Embedded Memory Blocks