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Iouliia Skliarova

Researcher at University of Aveiro

Publications -  156
Citations -  1169

Iouliia Skliarova is an academic researcher from University of Aveiro. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 16, co-authored 151 publications receiving 1079 citations.

Papers
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Proceedings ArticleDOI

Reconfigurable Digital Audio Mixer for Electroacoustic Music

TL;DR: The system MIAUDIO described in the paper allows using up to 8 input channels that can be mixed in real-time through 32 output speakers and has very low cost and was developed in relatively short time.
Journal ArticleDOI

Enriching Traditional Higher STEM Education with Online Teaching and Learning Practices: Students’ Perspective

TL;DR: In this paper , the authors aim to identify online teaching and learning practices that would be beneficial for blended and traditional on-campus education within STEM (Science, Technology, Engineering, and Mathematics) courses.
Proceedings ArticleDOI

Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware

TL;DR: The paper analyses and compares alternative iterative and recursive implementations of combinatorial search algorithms in hardware (in field-programmable gate arrays - FPGA, in particular) for Boolean satisfiability, binary matrix covering, and graph coloring.
Book ChapterDOI

Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers

TL;DR: In this paper, the authors describe two methods for the design of matrix-oriented SAT solvers based on data compression, one provides matrix compression in a host computer and decompression in an FPGA, and the second makes possible to execute operations required for solving the SAT problem over compressed matrices.
Journal ArticleDOI

A Survey of Network-Based Hardware Accelerators

Iouliia Skliarova
- 25 Mar 2022 - 
TL;DR: This review paper aims to analyze, compare, and discuss different approaches to implementing network-based hardware accelerators in FPGA and programmable SoC (Systems-on-Chip).