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Iouliia Skliarova

Researcher at University of Aveiro

Publications -  156
Citations -  1169

Iouliia Skliarova is an academic researcher from University of Aveiro. The author has contributed to research in topics: Field-programmable gate array & Reconfigurable computing. The author has an hindex of 16, co-authored 151 publications receiving 1079 citations.

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Proceedings ArticleDOI

FPGA-based systems in information and communication

TL;DR: This tutorial is intended to give introduction to FPGA-based systems, to illustrate advantages of these systems in terms of technical characteristics and economic aspects, to demonstrate design steps on practical examples, and to discuss potential benefits and case studies targeted to the scope of the conference.
Proceedings ArticleDOI

FPGA-based time and cost effective Hamming weight comparators for binary vectors

TL;DR: The paper suggests several, supplementing each other, Hamming weight counters and comparators based on optimized mapping of the circuits to FPGA look-up tables giving the best performance and the fewest resources compared to the best known alternatives.
Proceedings ArticleDOI

Methodology and international collaboration in teaching reconfigurable systems

TL;DR: The methodology includes e-learning tools (namely, tutorials, templates, and previously developed students' projects) combined with another methods that are: separation of given to students tasks on core and auxiliary components, and design based on interactions, virtualization, and communication with host computers.
Proceedings ArticleDOI

Exploiting FPGA-Based Architectures and Design Tools for Problems of Reconfigurable Computations

TL;DR: The paper presents an approach allowing the run-time modification of combinatorial computations via reloading the RAM-based configurable logic blocks of the FPGAs.
Proceedings ArticleDOI

Design tools for reconfigurable embedded systems

TL;DR: This paper describes the developed hardware/software tools, libraries and design methods for FPGA-based embedded systems which include a kernel prototyping board with the Xilinx Spartan 3 FPGAs, and programs enabling the designers to partition the functionality of the developed system between software, running on a PC computer, and hardware, implemented in FPN.