There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

To study the operational behaviour of λ-terms, we will use the denotational (mathematical) approach. A denotational semantics for a language is based on the choice of a space of semantics values, or denotations, where terms are to be interpreted. Choosing a space with nice mathematical properties can help in proving the semantic properties of terms, since to this aim standard mathematical techniques can be used.

λ Δ -Models

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

Abstract. The paper suggests and describes two architectures for parallel data sort. The first architecture is applicable to large data sets and it combines three stages of data processing: data sorting in hardware (in a Field-Programmable Gate Arrays – FPGA), merging preliminary sorted blocks in hardware (in the FPGA), and merging large subsets received from the FPGA in general-purpose software. Data exchange between the FPGA and a general-purpose computer is organized through a fast Peripheral Component Interconnect (PCI) express bus. The second architecture is applicable to small data sets and it enables sorting to be done at the time of data acquisition, i.e. as soon as the last data item is received, the sorted items can be transferred immediately. The results of experiments clearly demonstrate the advantages of the proposed architectures that permit the reduction of the required hardware resources and increasing throughput compared to the results reported in publications and software functions targeted to data sorting.

Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems

The paper shows that fast counting non-zero components (Hamming weights) and comparing the results (Hamming distances) in large sets of data items is important for numerous practical applications and this problem has been broadly investigated by software and hardware designers. It is frequently referenced as population or vector set bits count (or simply popcount). This paper is dedicated to multi-core FPGA-based accelerators that compute Hamming weights/distances and compare the results with fixed thresholds and variable bounds. It is shown that widely available in contemporary FPGAs digital signal processing slices may be used efficiently and they provide the fastest and the less resource consuming solutions. A thorough analysis and comparison with the best known alternatives both in hardware and in software is presented and supported by numerous experiments in the recent Nexys-4, ZedBoard and ZyBo prototyping systems. Complete hardware description language (VHDL) specifications for core components are given ready to be synthesized, implemented, tested and evaluated. Experiments with the proposed designs clearly demonstrate significant speed-up comparing to known hardware/software alternatives.

Multi-core DSP-based Vector Set Bits Counters/Comparators

Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and chemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important. The paper suggests two types of hardware accelerators that are 1 designed in FPGAs and 2 implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. A three-level system architecture that includes a general-purpose computer, the problem-specific ARM, and reconfigurable hardware is then proposed. The results of experiments and comparisons with existing benchmarks demonstrate that although throughput of popcount computations is increased in FPGA-based designs interacting with general-purpose computers, communication overheads in experiments with PCI express are significant and actual advantages can be gained if not only popcount but also other types of relevant computations are implemented in hardware. The comparison of software/hardware designs for Zynq-7000 all programmable systems-on-chip with pure software implementations in the same Zynq-7000 devices demonstrates increase in performance by a factor ranging from 5 to 19 taking into account all the involved communication overheads between the programmable logic and the processing systems.

/pdf/on-chip-reconfigurable-hardware-accelerators-for-popcount-2fw5xgls1u.pdf

On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

The paper presents the results of the analysis of different models that are used in problems of combinatorial optimization, such as graphs, sets, discrete matrices, and Boolean functions. It is shown that these models can be mutually converted one into another. Many examples of typical combinatorial tasks, which appear at different steps of the design of digital devices, are considered. The majority of these tasks can be solved with the aid of the presented models and the respective combinatorial methods. Finally, different ways of implementation of combinatorial algorithms are analyzed.

Modelos matemáticos e problemas de optimização combinatória

Digital system design constitutes an essential part of engineering education. Many universities worldwide target the respective courses to field-programmable gate arrays and the relevant design flow. Recent programmable systems-on-chip integrating a processor-based computing system and a programmable logic rely on quite a different design philosophy constituting a new challenge for future engineers. These new trends have to be certainly reflected in the pedagogical activity so that the current students would, in a few years, satisfy the growing industry requirements. In this paper we analyze the new design flow and explore in detail one particular part of it: a possibility of directly generating hardware modules from software specifications through high-level synthesis. The reported teaching method is to be applied in two tightly collaborating Universities: University of Aveiro in Portugal and Tallinn University of Technology in Estonia.

Iouliia Skliarova

Papers

Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems

Multi-core DSP-based Vector Set Bits Counters/Comparators

On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

Modelos matemáticos e problemas de optimização combinatória

Integration of high-level synthesis to the courses on reconfigurable digital systems